349 lines
9.0 KiB
C
349 lines
9.0 KiB
C
/*
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* sound\soc\sunxi\sunxi_mad.h
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* (C) Copyright 2018-2023
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Wolfgang <qinzhenying@allwinnertech.com>
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*
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* some simple description for this code
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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*/
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#ifndef __SUNXI_MAD_H
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#define __SUNXI_MAD_H
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#include "sunxi-pcm.h"
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#undef SUNXI_MAD_DEBUG_INFO
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#ifdef CONFIG_ARCH_SUN8IW18
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/* SUN8IW18P1 should not be setup. */
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#undef SUNXI_MAD_NETLINK_USE
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#undef SUNXI_MAD_NETLINK_APP_PAUSE_USE
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#undef SUNXI_MAD_NETLINK_APP_PAUSE_USE
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#undef MAD_CLK_ALWAYS_ON
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//#undef SUNXI_LPSD_CLK_ALWAYS_ON
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#define SUNXI_LPSD_CLK_ALWAYS_ON
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#undef SUNXI_MAD_DATA_INT_USE
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#define SUNXI_MAD_SRAM_SUSPEND_RESET
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#endif
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struct sunxi_mad_priv {
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struct sunxi_mad_info *sunxi_mad;
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unsigned int mad_bind;
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/* mad params */
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unsigned int sample_rate;
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unsigned int lpsd_chan_sel;
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unsigned int mad_standby_chan_sel;
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unsigned int audio_src_chan_num;
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};
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enum mad_sram_bmode {
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MAD_SRAM_BMODE_NORMAL = 0,
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MAD_SRAM_BMODE_BOOT = 1,
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};
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enum mad_path_sel {
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MAD_PATH_NONE = 0,
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MAD_PATH_I2S0 = 1,
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MAD_PATH_CODEC = 2,
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MAD_PATH_DMIC = 3,
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MAD_PATH_I2S1 = 4,
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MAD_PATH_I2S2 = 5,
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};
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#ifdef CONFIG_ARCH_SUN8IW18
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#undef SUNXI_MAD_DATA_INT_USE
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#endif
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#define EVT_MAX_SIZE 256
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#define SUNXI_NETLINK_MAD 30
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/*------------------MAD register definition--------------------*/
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#define SUNXI_MAD_CTRL 0x00
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#define SUNXI_MAD_SRAM_POINT 0x04
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#define SUNXI_MAD_SRAM_SIZE 0x08
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#define SUNXI_MAD_SRAM_RD_POINT 0x0C
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#define SUNXI_MAD_RD_SIZE 0x10
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#define SUNXI_MAD_SRAM_STORE_TH 0x14
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#define SUNXI_MAD_SRAM_AHB1_TX_TH 0x18
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#define SUNXI_MAD_SRAM_AHB1_RX_TH 0x1C
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#define SUNXI_MAD_SRAM_WAKE_BACK_DATA 0x20
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#define SUNXI_MAD_AD_PATH_SEL 0x24
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#define SUNXI_MAD_LPSD_AD_SYNC_FC 0x28
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#define SUNXI_MAD_LPSD_TH 0x2C
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#define SUNXI_MAD_LPSD_RRUN 0x30
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#define SUNXI_MAD_LPSD_RSTOP 0x34
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#define SUNXI_MAD_LPSD_ECNT 0x38
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#define SUNXI_MAD_SRAM_CH_MASK 0x3C
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#define SUNXI_MAD_LPSD_CH_MASK 0x40
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#define SUNXI_MAD_SRAM_SEC_REGION_REG 0x44
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#define SUNXI_MAD_SRAM_PRE_DSIZE 0x48
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#define SUNXI_MAD_DMA_TF_SIZE 0x4C
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#define SUNXI_MAD_DMA_TF_LAST_SIZE 0x50
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#define SUNXI_MAD_INT_ST_CLR 0x60
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#define SUNXI_MAD_INT_MASK 0x64
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#define SUNXI_MAD_STA 0x68
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#define SUNXI_MAD_DEBUG 0x6C
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/*SUNXI_MAD_CTRL: 0x00*/
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#define AUDIO_DATA_SYNC_FRC 7
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#define SRAM_RST 6
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#define DMA_TYPE 5
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#define DMA_EN 4
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#define CPUS_RD_DONE 3
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#define GO_ON_SLEEP 2
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#define KEY_WORD_OK 1
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#define MAD_EN 0
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/* DMA type*/
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#define DMA_TYPE_MASK 0x1
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#define DMA_TYPE_IO 0x1
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#define DMA_TYPE_MEM 0x0
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/*SUNXI_MAD_SRAM_POINT: 0x04*/
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#define MAD_SRAM_PONT 0
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/*SUNXI_MAD_SRAM_SIZE: 0x08*/
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#define MAD_SRAM_SIZE 0
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/*SUNXI_MAD_SRAM_RD_POINT: 0x0C*/
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#define MAD_SRAM_RD_POINT 0
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/*SUNXI_MAD_SRAM_RD_SIZE(unit: half word): 0x10*/
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#define MAD_SRAM_RD_SIZE 0
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/*SUNXI_MAD_SRAM_STORE_TH(unit: half word): 0x14*/
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#define MAD_SRAM_STORE_TH 0
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/*SUNXI_MAD_SRAM_AHB1_TX_TH(unit: byte): 0x18*/
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#define MAD_SRAM_AHB1_TX_TH 0
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/*SUNXI_MAD_SRAM_AHB1_RX_TH(unit: byte): 0x1C*/
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#define MAD_SRAM_AHB1_RX_TH 0
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/*SUNXI_MAD_SRAM_WAKE_BACK_DATA(unit: frame): 0x20*/
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#define MAD_SRAM_WAKE_BACK_DATA 0
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/*SUNXI_MAD_AD_PATH_SEL: 0x24*/
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#define MAD_AD_PATH_SEL 0
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#define MAD_AD_PATH_SEL_MASK 0xF
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/*MAD audio src sel*/
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#define MAD_AD_PATH_NO_SRC 0x0
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#define MAD_AD_PATH_I2S0_SRC 0x1
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#define MAD_AD_PATH_CODEC_SRC 0x2
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#define MAD_AD_PATH_DMIC_SRC 0x3
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#define MAD_AD_PATH_I2S1_SRC 0x4
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#define MAD_AD_PATH_I2S2_SRC 0x5
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/*SUNXI_MAD_LPSD_AD_SYNC_FC: 0x28*/
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#define MAD_LPSD_AD_SYNC_FC 0
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#define MAD_LPSD_AD_SYNC_FC_DEF 0X20
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/*SUNXI_MAD_LPSD_TH: 0x2C*/
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#define MAD_LPSD_TH 0
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/*SUNXI_MAD_LPSD_RRUN: 0x30*/
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#define MAD_LPSD_RRUN 0
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/*SUNXI_MAD_LPSD_RSTOP: 0x34*/
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#define MAD_LPSD_RSTOP 0
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/*SUNXI_MAD_LPSD_ECNT: 0x38*/
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#define MAD_LPSD_ECNT 0
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/*SUNXI_MAD_SRAM_CH_MASK: 0x3C*/
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#define MAD_CH_CHANGE_EN 30
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#define MAD_CH_COM_NUM 26
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#define MAD_AD_SRC_CH_NUM 21
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#define MAD_SRAM_CH_NUM 16
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#define MAD_SRAM_CH_MASK 0
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#define MAD_SRAM_CH_NUM_MASK 0x1F
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/*MAD channel change sel*/
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#define MAD_CH_COM_NUM_MASK 0xF
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#define MAD_CH_COM_NON 0x0
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#define MAD_CH_COM_2CH_TO_4CH 0x1
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#define MAD_CH_COM_2CH_TO_6CH 0x2
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#define MAD_CH_COM_2CH_TO_8CH 0x3
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#define MAD_CH_COM_4CH_TO_6CH 0x4
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#define MAD_CH_COM_4CH_TO_8CH 0x5
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/*SUNXI_MAD_LPSD_CH_MASK: 0x40*/
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#define MAD_LPSD_DCBLOCK_EN 20
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#define MAD_LPSD_CH_NUM 16
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#define MAD_LPSD_CH_MASK 0
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/*LPSD receive 0/1 audio channel mask*/
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#define MAD_LPSD_CH_NUM_MASK 0xF
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/*LPSD AUDIO channel num sel*/
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#define MAD_LPSD_CH_NUM_NON 0x0
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#define MAD_LPSD_CH_NUM_1CH 0x1
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/*SUNXI_MAD_SRAM_SEC_REGION: 0x44*/
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#define MAD_SRAM_SEC_REGION 0
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/*SUNXI_MAD_SRAM_PRE_DATA_SIZE(unit: half word): 0x48*/
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#define MAD_SRAM_PRE_DATA_SIZE 0
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/*SUNXI_MAD_DMA_TF_SIZE: 0x4C*/
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#define MAD_DMA_TF_SIZE 0
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/*SUNXI_MAD_DMA_TF_LAST_SIZE: 0x50*/
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#define MAD_DMA_TF_LAST_SIZE 0
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/*SUNXI_MAD_INT_ST_CLR: 0x60*/
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#define DATA_REQ_INT 1
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#define WAKE_INT 0
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/*SUNXI_MAD_INT_MASK: 0x64*/
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#define DATA_REQ_INT_MASK 1
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#define MAD_REQ_INT_MASK 0
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/*SUNXI_MAD_STATE_REG: 0x68*/
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#define MAD_LPSD_STAT 8
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#define MAD_STATE 4
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#define MAD_SRAM_FULL 2
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#define MAD_SRAM_EMPTY 1
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#define MAD_RUN 0
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/*MAD STATE(read only)*/
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#define MAD_STATE_IDLE 0x0
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#define MAD_STATE_WAIT 0x1
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#define MAD_STATE_RUN 0x2
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#define MAD_STATE_NORMAL 0x4
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/*SUNXI_MAD_DEBUG: 0x6C*/
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#define MAD_CFG_ERR 4
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#define MAD_SRAM_FULL_ERR 3
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#define MAD_SRAM_EMPTY_ERR 2
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#define DATA_SRAM_ADDR_ERR 1
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#define MAD_SRAM_SEC_ERR 0
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/*MAD_CFG_ERR mask*/
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#define MAD_CFG_ERR_MASK 0x3
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/* for mad clk*/
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#define MAD_SRAM_BMODE_CTRL 24
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#define SRAM_BMODE_CTRL_REG 0x3000004
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enum sunxi_mad_sram_reset_flag {
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SUNXI_MAD_SRAM_RESET_IDLE = 0,
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SUNXI_MAD_SRAM_RESET_START = 1,
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SUNXI_MAD_SRAM_RESET_END = 2,
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};
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enum sunxi_mad_status {
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SUNXI_MAD_OPEN = 0,
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SUNXI_MAD_PARAMS = 1,
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SUNXI_MAD_SUSPEND = 2,
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SUNXI_MAD_RESUME = 3,
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SUNXI_MAD_CLOSE = 4,
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};
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enum sunxi_mad_dma_type {
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SUNXI_MAD_DMA_MEM = 0,
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SUNXI_MAD_DMA_IO = 1,
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};
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enum sunxi_mad_standby_flag {
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/* bit0 for sram IO type when standby */
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SUNXI_MAD_STANDBY_SRAM_MEM = 0x1,
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};
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enum sunxi_mad_wakeup_flag {
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/* bit0 for wakeup source */
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SUNXI_MAD_WAKEUP_OFF = 0x0,
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SUNXI_MAD_WAKEUP_ON = 0x1,
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/* bit1 for wakeup use or no */
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SUNXI_MAD_WAKEUP_USE = 0x2,
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/* bit2 for lpsd wakeup */
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SUNXI_MAD_WAKEUP_LPSD_IRQ = 0x4,
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/* bit3 for mad irq wakeup */
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SUNXI_MAD_WAKEUP_MAD_IRQ = 0x8,
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/* bit4 for other irq wakeup */
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SUNXI_MAD_WAKEUP_OTHER = 0x10,
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};
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struct sunxi_mad_info {
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struct device *dev;
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struct clk *mad_clk;
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struct clk *mad_cfg_clk;
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struct clk *mad_ad_clk;
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struct clk *lpsd_clk;
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struct clk *pll_clk;
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struct clk *hosc_clk;
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unsigned int pll_audio_src_used;
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unsigned int hosc_src_used;
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void __iomem *membase;
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struct regmap *regmap;
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unsigned int mad_irq;
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unsigned int lpsd_irq;
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unsigned int sram_rd_point;
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unsigned int mad_bind;
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unsigned int audio_src_path;
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unsigned int audio_src_chan_num;
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unsigned int standby_chan_sel;
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unsigned int lpsd_chan_sel;
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int status;
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struct timeval suspend_tv;
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unsigned int wakeup_flag;
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unsigned int suspend_flag;
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unsigned int sram_reset_flag;
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int standby_sram_type;
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int wakeup_irq_en;
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spinlock_t resume_spin;
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struct work_struct ws_resume;
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struct work_struct ws_suspend;
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};
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extern int sunxi_mad_sram_set_reset_flag(enum sunxi_mad_sram_reset_flag reset_flag);
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extern enum sunxi_mad_sram_reset_flag sunxi_mad_sram_get_reset_flag(void);
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extern int sunxi_mad_sram_wait_reset_flag(enum sunxi_mad_sram_reset_flag reset_flag,
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unsigned int time_out_msecond);
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extern void sunxi_mad_sram_chan_params(unsigned int mad_channels);
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extern struct sunxi_mad_info *sunxi_mad_get_mad_info(void);
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extern void sunxi_mad_clk_enable(bool val);
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extern void sunxi_mad_ad_clk_enable(bool val);
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extern void sunxi_mad_cfg_clk_enable(bool val);
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extern void sunxi_mad_module_clk_enable(bool val);
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extern void sunxi_lpsd_clk_enable(bool val);
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/* for mad interrupt */
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extern void sunxi_lpsd_int_stat_clr(void);
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extern void sunxi_mad_set_lpsdreq(bool enable);
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extern void sunxi_mad_set_datareq(bool enable);
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/* for mad init */
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extern int sunxi_mad_open(void);
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extern int sunxi_mad_close(void);
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extern void sunxi_mad_sram_init(void);
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extern void sunxi_mad_lpsd_init(void);
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extern void sunxi_sram_ahb1_threshole_init(void);
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extern void sunxi_mad_standby_chan_sel(unsigned int num);
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extern void sunxi_lpsd_chan_sel(unsigned int num);
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extern void sunxi_mad_audio_src_chan_num(unsigned int num);
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extern void sunxi_sram_dma_config(struct sunxi_dma_params *capture_dma_param);
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extern int sunxi_mad_hw_params(unsigned int mad_channels, unsigned int sample_rate);
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extern int sunxi_mad_audio_source_sel(unsigned int path_sel, unsigned int enable);
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extern int sunxi_mad_suspend_external(void);
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extern int sunxi_mad_resume_external(void);
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extern void sunxi_mad_dma_enable(bool enable);
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extern void sunxi_mad_dma_type(enum sunxi_mad_dma_type dma_type);
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extern int sunxi_mad_enable(bool enable);
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extern void sunxi_mad_set_go_on_sleep(bool enable);
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extern void sunxi_mad_sram_set_reset_bit(void);
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#endif /* SUNXI_MAD_H */
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