158 lines
3.4 KiB
C
158 lines
3.4 KiB
C
/*
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* (C) Copyright 2013-2016
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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*
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*/
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/*
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* COM1 NS16550 support
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* originally from linux source (arch/powerpc/boot/ns16550.c)
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* modified to use CONFIG_SYS_ISA_MEM and new defines
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <arch/uart.h>
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#include <arch/gpio.h>
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#include <arch/clock.h>
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#define thr rbr
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#define dll rbr
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#define dlh ier
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#define iir fcr
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static serial_hw_t *serial_ctrl_base;
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#ifdef CFG_GET_WKSRC
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static serial_hw_t *serial_ctrl_M0_base;
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#define M0_UART_BAUD 9600
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void sunxi_serial_M0_init(int uart_port, void *gpio_cfg, int gpio_max)
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{
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u32 uart_clk;
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void __iomem *uart0_base = sunxi_get_iobase(SUNXI_UART0_BASE);
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#ifdef FPGA_PLATFORM
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normal_gpio_set_t fpga_uart_gpio[2] = {
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{2, 9, 3, 1, 1, 0, {0} }, /* PB9: 3--RX */
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{2, 8, 3, 1, 1, 0, {0} }, /* PB8: 3--TX */
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};
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#endif
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sunxi_clock_init_uart(uart_port);
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/* gpio */
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#ifdef FPGA_PLATFORM
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boot_set_gpio(fpga_uart_gpio, gpio_max, 1);
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#else
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boot_set_gpio(gpio_cfg, gpio_max, 1);
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#endif
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/* uart init */
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serial_ctrl_M0_base = (serial_hw_t *)(uart0_base + uart_port * CCM_UART_ADDR_OFFSET);
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serial_ctrl_M0_base->mcr = 0x3;
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uart_clk = (24000000 + 8 * M0_UART_BAUD)/(16 * M0_UART_BAUD);
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serial_ctrl_M0_base->lcr |= 0x80;
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serial_ctrl_M0_base->dlh = uart_clk>>8;
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serial_ctrl_M0_base->dll = uart_clk&0xff;
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serial_ctrl_M0_base->lcr &= ~0x80;
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serial_ctrl_M0_base->lcr = ((PARITY&0x03)<<3) | ((STOP&0x01)<<2) | (DLEN&0x03);
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serial_ctrl_M0_base->fcr = 0x7;
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return;
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}
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int has_sunxi_serial_M0_send(unsigned char *buff, size_t len)
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{
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u32 start= 0;
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int i;
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for (i = 0; i < len; i++)
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{
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start = get_sys_ticks();
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while ((serial_ctrl_M0_base->lsr & (1 << 6)) == 0)
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{
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if (get_sys_ticks() - start > 30)
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{
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pr_emerg("can't send cmd\n");
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return -1;
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}
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}
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serial_ctrl_M0_base->thr = buff[i];
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}
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return i;
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}
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int has_sunxi_serial_M0_get(unsigned char *buff, size_t len)
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{
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u32 start= 0;
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int i;
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for (i = 0; i < len; i++)
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{
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start = get_sys_ticks();
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while ((serial_ctrl_M0_base->lsr & 1) == 0)
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{
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if (get_sys_ticks() - start > 30)
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{
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pr_emerg("can't get wksrc\n");
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return -1;
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}
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}
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buff[i] = serial_ctrl_M0_base->rbr;
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}
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return i;
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}
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#endif
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void sunxi_serial_init(int uart_port, void *gpio_cfg, int gpio_max)
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{
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u32 uart_clk;
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void __iomem *uart0_base = sunxi_get_iobase(SUNXI_UART0_BASE);
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#ifdef FPGA_PLATFORM
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normal_gpio_set_t fpga_uart_gpio[2] = {
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{2, 9, 3, 1, 1, 0, {0} }, /* PB9: 3--RX */
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{2, 8, 3, 1, 1, 0, {0} }, /* PB8: 3--TX */
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};
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#endif
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sunxi_clock_init_uart(uart_port);
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/* gpio */
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#ifdef FPGA_PLATFORM
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boot_set_gpio(fpga_uart_gpio, gpio_max, 1);
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#else
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boot_set_gpio(gpio_cfg, gpio_max, 1);
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#endif
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/* uart init */
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serial_ctrl_base = (serial_hw_t *)(uart0_base + uart_port * CCM_UART_ADDR_OFFSET);
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serial_ctrl_base->mcr = 0x3;
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uart_clk = (24000000 + 8 * UART_BAUD)/(16 * UART_BAUD);
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serial_ctrl_base->lcr |= 0x80;
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serial_ctrl_base->dlh = uart_clk>>8;
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serial_ctrl_base->dll = uart_clk&0xff;
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serial_ctrl_base->lcr &= ~0x80;
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serial_ctrl_base->lcr = ((PARITY&0x03)<<3) | ((STOP&0x01)<<2) | (DLEN&0x03);
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serial_ctrl_base->fcr = 0x7;
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return;
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}
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void sunxi_serial_putc (char c)
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{
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while ((serial_ctrl_base->lsr & (1 << 6)) == 0)
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;
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serial_ctrl_base->thr = c;
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}
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char sunxi_serial_getc (void)
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{
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while ((serial_ctrl_base->lsr & 1) == 0)
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;
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return serial_ctrl_base->rbr;
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}
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int sunxi_serial_tstc (void)
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{
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return serial_ctrl_base->lsr & 1;
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}
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