285 lines
7.2 KiB
C
285 lines
7.2 KiB
C
/*
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* (C) Copyright 2022-2025
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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*
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* lujianliang <lujianliang@allwinnertech.com>
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <arch/spi.h>
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#include <arch/spi-mem.h>
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#include "spif-sunxi.h"
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#ifdef CFG_SUNXI_SPIF
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//extern void spif_print_descriptor(struct spif_descriptor_op *spif_op);
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static int spif_select_buswidth(u32 buswidth)
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{
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int width = 0;
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switch (buswidth) {
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case SPIF_SINGLE_MODE:
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width = 0;
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break;
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case SPIF_DUEL_MODE:
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width = 1;
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break;
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case SPIF_QUAD_MODE:
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width = 2;
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break;
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case SPIF_OCTAL_MODE:
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width = 3;
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break;
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default:
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printf("Parameter error with buswidth:%d\n", buswidth);
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}
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return width;
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}
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void *malloc_align(unsigned int len, unsigned int align, void *buf)
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{
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unsigned int alignd;
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buf = malloc(len + align - 1);
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if (!buf)
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return NULL;
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alignd = ((unsigned int)buf + align - 1) & ~(align - 1);
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//printf("malloc len:%d addr:%x align:%x\n", (len + align - 1), (unsigned int)buf, alignd);
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return (void *)alignd;
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}
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int spif_mem_exec_op(const struct spi_mem_op *op)
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{
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int ret;
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void *desc_cache = NULL;
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struct spif_descriptor_op *spif_op;
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uint cache_buf[CONFIG_SYS_CACHELINE_SIZE] __aligned(CONFIG_SYS_CACHELINE_SIZE);
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uint desc_count = ((op->data.nbytes + SPIF_MAX_TRANS_NUM - 1) / SPIF_MAX_TRANS_NUM) + 1;
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uint desc_size = desc_count * sizeof(struct spif_descriptor_op);
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spif_op = malloc_align(desc_size, CONFIG_SYS_CACHELINE_SIZE, desc_cache);
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if (!spif_op) {
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printf("malloc align error");
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return -1;
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}
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memset(spif_op, 0, desc_size);
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memset(cache_buf, 0, CONFIG_SYS_CACHELINE_SIZE);
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/* set hburst type */
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spif_op->hburst_rw_flag &= ~HBURST_TYPE;
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spif_op->hburst_rw_flag |= HBURST_INCR16_TYPE;
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/* the last one descriptor */
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spif_op->hburst_rw_flag |= DMA_FINISH_FLASG;
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/* set DMA block len mode */
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spif_op->block_data_len &= ~DMA_BLK_LEN;
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spif_op->block_data_len |= DMA_BLK_LEN_64B;
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spif_op->addr_dummy_data_count |= SPIF_DES_NORMAL_EN;
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/* dispose cmd */
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if (op->cmd.opcode) {
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spif_op->trans_phase |= SPIF_CMD_TRANS_EN;
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spif_op->cmd_mode_buswidth |= op->cmd.opcode << SPIF_CMD_OPCODE_POS;
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/* set cmd buswidth */
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spif_op->cmd_mode_buswidth |=
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spif_select_buswidth(op->cmd.buswidth) << SPIF_CMD_TRANS_POS;
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if (op->cmd.buswidth != 1)
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spif_op->cmd_mode_buswidth |=
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spif_select_buswidth(op->cmd.buswidth) <<
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SPIF_DATA_TRANS_POS;
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}
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/* dispose addr */
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if (op->addr.nbytes) {
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spif_op->trans_phase |= SPIF_ADDR_TRANS_EN;
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spif_op->flash_addr = op->addr.val;
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if (op->addr.nbytes == 4) //set 4byte addr mode
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spif_op->addr_dummy_data_count |= SPIF_ADDR_SIZE_MODE;
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/* set addr buswidth */
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spif_op->cmd_mode_buswidth |=
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spif_select_buswidth(op->addr.buswidth) <<
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SPIF_ADDR_TRANS_POS;
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}
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/* dispose mode */
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if (op->mode.val) {
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spif_op->trans_phase |= SPIF_MODE_TRANS_EN;
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spif_op->cmd_mode_buswidth |=
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*(u8 *)op->mode.val << SPIF_MODE_OPCODE_POS;
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/* set addr buswidth */
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spif_op->cmd_mode_buswidth |=
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spif_select_buswidth(op->mode.buswidth) <<
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SPIF_MODE_TRANS_POS;
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}
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/* dispose dummy */
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if (op->dummy.cycle) {
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spif_op->trans_phase |= SPIF_DUMMY_TRANS_EN;
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spif_op->addr_dummy_data_count |=
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(op->dummy.cycle << SPIF_DUMMY_NUM_POS);
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}
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/* dispose data */
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if (op->data.nbytes) {
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/* set data buswidth */
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spif_op->cmd_mode_buswidth |=
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spif_select_buswidth(op->data.buswidth) << SPIF_DATA_TRANS_POS;
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if (op->data.dir == SPI_MEM_DATA_IN) {
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spif_op->trans_phase |= SPIF_RX_TRANS_EN;
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if (op->data.nbytes < SPIF_MIN_TRANS_NUM)
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spif_op->data_addr = (u32)cache_buf;
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else
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spif_op->data_addr = (u32)op->data.buf.in;
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/* Write:1 DMA Write to dram */
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spif_op->hburst_rw_flag |= DMA_RW_PROCESS;
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} else {
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spif_op->trans_phase |= SPIF_TX_TRANS_EN;
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spif_op->data_addr = (u32)op->data.buf.out;
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/* Read:0 DMA read for dram */
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spif_op->hburst_rw_flag &= ~DMA_RW_PROCESS;
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}
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if (op->data.nbytes < SPIF_MIN_TRANS_NUM &&
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op->data.dir == SPI_MEM_DATA_IN) {
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spif_op->addr_dummy_data_count |=
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SPIF_MIN_TRANS_NUM << SPIF_DATA_NUM_POS;
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spif_op->block_data_len |=
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SPIF_MIN_TRANS_NUM << SPIF_DATA_NUM_POS;
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} else if (op->data.nbytes <= SPIF_MAX_TRANS_NUM) {
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spif_op->addr_dummy_data_count |=
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op->data.nbytes << SPIF_DATA_NUM_POS;
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spif_op->block_data_len |=
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op->data.nbytes << SPIF_DATA_NUM_POS;
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} else {
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unsigned int total_len = op->data.nbytes;
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struct spif_descriptor_op *current_op = spif_op;
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spif_op->addr_dummy_data_count |=
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SPIF_MAX_TRANS_NUM << SPIF_DATA_NUM_POS;
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spif_op->block_data_len |=
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SPIF_MAX_TRANS_NUM << SPIF_DATA_NUM_POS;
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spif_op->hburst_rw_flag &= ~DMA_FINISH_FLASG;
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total_len -= SPIF_MAX_TRANS_NUM;
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while (total_len) {
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struct spif_descriptor_op *next_op = current_op + 1;
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memcpy(next_op, current_op, sizeof(struct spif_descriptor_op));
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current_op->next_des_addr = (unsigned int)next_op;
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//spif_print_descriptor(current_op);
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next_op->addr_dummy_data_count &= ~DMA_DATA_LEN;
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next_op->block_data_len &= ~DMA_DATA_LEN;
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if (total_len > SPIF_MAX_TRANS_NUM) {
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next_op->addr_dummy_data_count |=
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SPIF_MAX_TRANS_NUM << SPIF_DATA_NUM_POS;
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next_op->block_data_len |=
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SPIF_MAX_TRANS_NUM << SPIF_DATA_NUM_POS;
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total_len -= SPIF_MAX_TRANS_NUM;
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} else {
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next_op->addr_dummy_data_count |=
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total_len << SPIF_DATA_NUM_POS;
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next_op->block_data_len |=
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total_len << SPIF_DATA_NUM_POS;
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next_op->hburst_rw_flag |= DMA_FINISH_FLASG;
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next_op->next_des_addr = 0;
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total_len = 0;
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}
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next_op->data_addr =
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current_op->data_addr + SPIF_MAX_TRANS_NUM;
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next_op->flash_addr =
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current_op->flash_addr + SPIF_MAX_TRANS_NUM;
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current_op = next_op;
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}
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//spif_print_descriptor(current_op);
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}
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}
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ret = spif_xfer(spif_op, op->data.nbytes);
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if (op->data.nbytes < SPIF_MIN_TRANS_NUM &&
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op->data.dir == SPI_MEM_DATA_IN)
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memcpy((void *)op->data.buf.in, (const void *)cache_buf,
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op->data.nbytes);
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if (desc_cache)
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free(desc_cache);
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return ret;
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}
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#endif /* CFG_SUNXI_SPIF */
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int spi_mem_exec_op(const struct spi_mem_op *op)
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{
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#ifdef CFG_SUNXI_SPIF
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return spif_mem_exec_op(op);
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#else
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unsigned int pos = 0;
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const u8 *tx_buf = NULL;
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u8 *rx_buf = NULL;
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u8 *op_buf;
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int op_len;
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int ret;
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int i;
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/* convert the dummy cycles to the number of bytes */
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int dummy_nbytes = (op->dummy.cycle * op->dummy.buswidth) / 8;
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if (op->data.nbytes) {
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if (op->data.dir == SPI_MEM_DATA_IN)
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rx_buf = op->data.buf.in;
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else
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tx_buf = op->data.buf.out;
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}
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op_len = sizeof(op->cmd.opcode) + op->addr.nbytes + dummy_nbytes;
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if (tx_buf)
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op_buf = malloc(op_len + op->data.nbytes);
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else
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op_buf = malloc(op_len);
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if (!op_buf) {
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return -1;
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}
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op_buf[pos++] = op->cmd.opcode;
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if (op->addr.nbytes) {
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for (i = 0; i < op->addr.nbytes; i++)
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op_buf[pos + i] = op->addr.val >>
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(8 * (op->addr.nbytes - i - 1));
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pos += op->addr.nbytes;
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}
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if (op->dummy.cycle)
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memset(op_buf + pos, 0xff, dummy_nbytes);
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if (tx_buf) {
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op_len += op->data.nbytes;
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memcpy(op_buf, tx_buf, op->data.nbytes);
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ret = spi_xfer(op->data.nbytes, op_buf, 0, NULL);
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if (ret)
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goto free_op_buf;
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} else {
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ret = spi_xfer(op_len, op_buf, op->data.nbytes, rx_buf);
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if (ret)
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goto free_op_buf;
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}
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free_op_buf:
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free(op_buf);
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if (ret < 0)
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return ret;
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return 0;
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#endif /* CFG_SUNXI_SPIF */
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}
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