207 lines
7.3 KiB
C
207 lines
7.3 KiB
C
/*
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* drivers/spi/spif-sunxi.h
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*
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* Copyright (C) 2021 - 2024 Reuuimlla Limited
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* Lu Jian Liang <lujianliang@reuuimllatech.com>
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*
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* SUNXI SPIF Register Definition
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* 2021.12.1 <lujianliang@allwinnertech.com>
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* Adapt to support sun8iw21~future of Allwinner.
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*/
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#ifndef _SUNXI_SPIF_H_
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#define _SUNXI_SPIF_H_
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/*
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#define SPI_MODULE_NUM (4)
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#define SPI_FIFO_DEPTH (128)
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#define MAX_FIFU 64
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#define BULK_DATA_BOUNDARY 64
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#define SPI_MAX_FREQUENCY 100000000
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*/
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/* SPIF Global (Additional) Control Register Bit Fields & Masks,default value:0x0000_0080 */
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/* SPIF Registers offsets from peripheral base address */
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#define SPIF_VER_REG (0x00) /* version number register */
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#define SPIF_GC_REG (0x04) /* global control register */
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#define SPIF_GCA_REG (0x08) /* global additional control register */
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#define SPIF_TC_REG (0x0C) /* timing control register */
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#define SPIF_TDS_REG (0x10) /* timing delay state register */
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#define SPIF_INT_EN_REG (0x14) /* interrupt enable register */
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#define SPIF_INT_STA_REG (0x18) /* interrupt status register */
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#define SPIF_CSD_REG (0x1C) /* chipselect delay register */
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#define SPIF_PHC_REG (0x20) /* trans phase configure register */
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#define SPIF_TCF_REG (0x24) /* trans configure1 register */
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#define SPIF_TCS_REG (0x28) /* trans configure2 register */
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#define SPIF_TNM_REG (0x2C) /* trans number register */
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#define SPIF_PS_REG (0x30) /* prefetch state register */
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#define SPIF_PSA_REG (0x34) /* prefetch start address register */
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#define SPIF_PEA_REG (0x38) /* prefetch end address register */
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#define SPIF_PMA_REG (0x3C) /* prefetch map address register */
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#define SPIF_DMA_CTL_REG (0x40) /* DMA control register */
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#define SPIF_DSC_REG (0x44) /* DMA descriptor start address register */
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#define SPIF_DFT_REG (0x48) /* DQS FIFO trigger level register */
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#define SPIF_CFT_REG (0x4C) /* CDC FIFO trigger level register */
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#define SPIF_CFS_REG (0x50) /* CDC FIFO status register */
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#define SPIF_BAT_REG (0x54) /* Bit-Aligned tansfer configure register */
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#define SPIF_BAC_REG (0x58) /* Bit-Aligned clock configuration register */
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#define SPIF_TB_REG (0x5C) /* TX Bit register */
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#define SPIF_RB_REG (0x60) /* RX Bit register */
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#define SPIF_RXDATA_REG (0x200) /* prefetch RX data register */
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/* SPIF global control register bit fields & masks,default value:0x0000_0100 */
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#define SPIF_GC_CFG_MODE (0x1 << 0)
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#define SPIF_GC_DMA_MODE (1)
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#define SPIF_GC_CPU_MODE (0)
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#define SPIF_GC_ADDR_MAP_MODE (0x1 << 1)
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#define SPIF_GC_NMODE_EN (0x1 << 2)
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#define SPIF_GC_PMODE_EN (0x1 << 3)
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#define SPIF_GC_CPHA (0x1 << 4)
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#define SPIF_GC_CPOL (0x1 << 5)
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#define SPIF_GC_SS_MASK (0x3 << 6) /* SPIF chip select:00-SPI_SS0;01-SPI_SS1;10-SPI_SS2;11-SPI_SS3*/
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#define SPIF_GC_CS_POL (0x1 << 8)
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#define SPIF_GC_DUMMY_BIT_POL (0x1 << 9)
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#define SPIF_GC_DQS_RX_EN (0x1 << 10)
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#define SPIF_GC_HOLD_POL (0x1 << 12)
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#define SPIF_GC_HOLD_EN (0x1 << 13)
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#define SPIF_GC_WP_POL (0x1 << 14)
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#define SPIF_GC_WP_EN (0x1 << 15)
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#define SPIF_GC_DTR_EN (0x1 << 16)
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#define SPIF_GC_RX_CFG_FBS (0x1 << 17)
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#define SPIF_GC_TX_CFG_FBS (0x1 << 18)
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#define SPIF_GC_SS_BIT_POS (6)
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#define MSB_FIRST (0)
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#define LSB_FIRST (1)
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//SPIF_GCR:SPIF_MODE
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#define SPIF_MODE0 (0U << 4)
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#define SPIF_MODE1 (SPIF_GC_CPHA)
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#define SPIF_MODE2 (SPIF_GC_CPOL)
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#define SPIF_MODE3 (SPIF_GC_CPOL | SPIF_GC_CPHA)
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#define SPIF_MASK (3U << 4)
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#define SPIF_SCKT_DELAY_MODE (1U << 21)
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#define SPIF_DIGITAL_ANALOG_EN (1U << 20)
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#define SPIF_DIGITAL_DELAY (16)
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#define SPIF_DIGITAL_DELAY_MASK (7U << 16)
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#define SPIF_ANALOG_DL_SW_RX_EN (1U << 6)
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#define SPIF_ANALOG_DELAY (0)
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#define SPIF_ANALOG_DELAY_MASK (0x3F << 0)
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#define SPIF_GCA_SRST (0xf << 0)
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#define SPIF_FIFO_SRST (0x3 << 0)
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#define SPIF_DFT_DQS (0x6400)
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#define SPIF_CFT_CDC (0x64106410)
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#define SPIF_CSDA (5)
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#define SPIF_CSEOT (6)
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#define SPIF_CSSOT (6)
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#define SPIF_CSD_DEF ((SPIF_CSDA << 16) | (SPIF_CSEOT << 8) | SPIF_CSSOT)
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/* SPIF Timing Configure Register Bit Fields & Masks,default value:0x0000_0000 */
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#define SPIF_SAMP_DL_VAL_TX_POS (8)
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#define SPIF_SAMP_DL_VAL_RX_POS (0)
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#define SPIF_SCKR_DL_MODE_SEL (0x1 << 20)
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#define SPIF_CLK_SCKOUT_SRC_SEL (0x1 << 26)
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/* SPIF Interrupt status Register Bit Fields & Masks,default value:0x0000_0000 */
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#define DMA_TRANS_DONE_INT (0x1 << 24)
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/* SPIF Trans Phase Configure Register Bit Fields & Masks,default value:0x0000_0000 */
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#define SPIF_RX_TRANS_EN (0x1 << 8)
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#define SPIF_TX_TRANS_EN (0x1 << 12)
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#define SPIF_DUMMY_TRANS_EN (0x1 << 16)
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#define SPIF_MODE_TRANS_EN (0x1 << 20)
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#define SPIF_ADDR_TRANS_EN (0x1 << 24)
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#define SPIF_CMD_TRANS_EN (0x1 << 28)
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/* SPIF Trans Configure2 Register Bit Fields & Masks,default value:0x0000_0000 */
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#define SPIF_DATA_TRANS_POS (0)
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#define SPIF_MODE_TRANS_POS (4)
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#define SPIF_ADDR_TRANS_POS (8)
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#define SPIF_CMD_TRANS_POS (12)
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#define SPIF_MODE_OPCODE_POS (16)
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#define SPIF_CMD_OPCODE_POS (24)
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/* SPIF Trans Number Register Bit Fields & Masks,default value:0x0000_0000 */
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#define SPIF_ADDR_SIZE_MODE (0x1 << 24)
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#define SPIF_DUMMY_NUM_POS (16)
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#define SPIF_DATA_NUM_POS (0)
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/* SPIF DMA Control Register Bit Fields & Masks,default value:0x0000_0000 */
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#define CFG_DMA_START (1 << 0)
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#define DMA_DESCRIPTOR_LEN (32 << 4)
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/* DMA descriptor0 Bit Fields & Masks */
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#define HBURST_SINGLE_TYPE (0x0 << 4)
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#define HBURST_INCR4_TYPE (0x3 << 4)
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#define HBURST_INCR8_TYPE (0x5 << 4)
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#define HBURST_INCR16_TYPE (0x7 << 4)
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#define HBURST_TYPE (0x7 << 4)
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#define DMA_RW_PROCESS (0x1 << 1) /* 0:Read 1:Write */
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#define DMA_FINISH_FLASG (0x1 << 0) /* The Last One Descriptor */
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/* DMA descriptor1 Bit Fields & Masks */
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#define DMA_BLK_LEN_8B (0x0 << 16)
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#define DMA_BLK_LEN_16B (0x1 << 16)
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#define DMA_BLK_LEN_32B (0x2 << 16)
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#define DMA_BLK_LEN_64B (0x3 << 16)
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#define DMA_BLK_LEN (0xffff << 16)
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#define DMA_DATA_LEN_POS (0)
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#define DMA_DATA_LEN (0xffff)
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/* DMA descriptor7 Bit Fields & Masks */
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#define SPIF_DES_NORMAL_EN (0x1 << 28)
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#define SPIF_OCTAL_MODE (8)
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#define SPIF_QUAD_MODE (4)
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#define SPIF_DUEL_MODE (2)
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#define SPIF_SINGLE_MODE (1)
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#define SPIF_MIN_TRANS_NUM (8)
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#define SPIF_MAX_TRANS_NUM (4096)
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#define NOR_PAGE_SIZE (256)
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#define CONFIG_SYS_CACHELINE_SIZE 64
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#define SAMP_MODE_DL_DEFAULT 0xaaaaffff
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struct sunxi_spif_slave {
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uint32_t max_hz;
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uint32_t mode;
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int cs_bitmap;/* cs0- 0x1; cs1-0x2, cs0&cs1-0x3. */
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uint32_t base_addr;
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unsigned int right_sample_delay;
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unsigned int right_sample_mode;
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unsigned int rx_dtr_en;
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unsigned int tx_dtr_en;
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};
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struct spif_descriptor_op {
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u32 hburst_rw_flag;
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u32 block_data_len;
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u32 data_addr;
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u32 next_des_addr;
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u32 trans_phase;//0x20
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u32 flash_addr;//0x24
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u32 cmd_mode_buswidth;//0x28
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u32 addr_dummy_data_count;//0x2c
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};
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struct sunxi_spif_slave *get_sspif(void);
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int spif_xfer(struct spif_descriptor_op *spif_op, unsigned int data_len);
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int spif_init(void);
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void spif_exit(void);
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int set_spif_clk(void);
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void spif_samp_mode(void __iomem *base_addr, unsigned int status);
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void spif_samp_dl_sw_rx_status(void __iomem *base_addr, unsigned int status);
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void spif_set_sample_mode(void __iomem *base_addr, unsigned int mode);
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void spif_set_sample_delay(void __iomem *base_addr, unsigned int sample_delay);
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#endif
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