181 lines
5.7 KiB
C
181 lines
5.7 KiB
C
/*
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* (C) Copyright 2007-2015
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Jerry Wang <wangflord@allwinnertech.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __PLATFORM_H
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#define __PLATFORM_H
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#define SUNXI_CE_BASE (0x01c15000L)
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#define SUNXI_SS_BASE SUNXI_CE_BASE
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//CPUX
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#if defined(CONFIG_ARCH_SUN8IW7P1)
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#define SUNXI_CPUXCFG_BASE (0x01f01c00L)
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#elif defined(CONFIG_ARCH_SUN8IW11P1)
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#define SUNXI_CPUXCFG_BASE (0x01700000L)
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#endif
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//sys ctrl
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#define SUNXI_SYSCRL_BASE (0x01c00000L)
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#define SUNXI_CCM_BASE (0x01c20000L)
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#define SUNXI_DMA_BASE (0x01c02000L)
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#define SUNXI_MSGBOX_BASE (0X01C17000L)
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#define SUNXI_SPINLOCK_BASE (0X01C18000L)
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#define SUNXI_HSTMR_BASE (0x01c60000L)
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#if defined(CONFIG_ARCH_SUN8IW7P1)
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#define SUNXI_SID_BASE (0x01c14000L)
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#elif defined(CONFIG_ARCH_SUN8IW11P1)
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#define SUNXI_SID_BASE (0x01c1b000L)
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#endif
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#define SUNXI_SMC_BASE (0x01c1e000L)
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//todo:#define SUNXI_SPC_BASE (0X01C21400L)
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#define SUNXI_TIMER_BASE (0x01c20c00L)
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//todo:#define SUNXI_CNT64_BASE (0x03009C00L)
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#if defined(CONFIG_ARCH_SUN8IW7P1)
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#define SUNXI_PWM_BASE (0X01C21400L)
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#elif defined(CONFIG_ARCH_SUN8IW11P1)
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#define SUNXI_PWM_BASE (0X01C23400L)
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#endif
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#define SUNXI_PIO_BASE (0x01c20800L)
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//todo:#define SUNXI_PSI_BASE (0x0300C000L)
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//todo:#define SUNXI_DCU_BASE (0x03010000L)
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#define SUNXI_GIC_BASE (0x01c81000L)
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//todo:#define SUNXI_IOMMU_BASE (0x030F0000L)
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//storage
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#define SUNXI_DRAMCTL0_BASE (0x01c63000L)
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#define SUNXI_NFC_BASE (0x01c03000L)
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#define SUNXI_SMHC0_BASE (0x01c0f000L)
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#define SUNXI_SMHC1_BASE (0x01c10000L)
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#define SUNXI_SMHC2_BASE (0x01c11000L)
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//noraml
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#define SUNXI_UART0_BASE (0x01c28000L)
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#define SUNXI_UART1_BASE (0x01c28400L)
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#define SUNXI_UART2_BASE (0x01c28800L)
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#define SUNXI_UART3_BASE (0x01c28c00L)
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#define SUNXI_UART4_BASE (0x01c29000L)
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#define SUNXI_RTWI_BASE (0x01c2ac00L)
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#define SUNXI_TWI0_BASE (0x01c2ac00L)
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#define SUNXI_TWI1_BASE (0x01c2b000L)
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#define SUNXI_TWI2_BASE (0x01c2b400L)
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#define SUNXI_TWI3_BASE (0x01c2b800L)
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//todo:#define SUNXI_SCR0_BASE (0x05005000L)
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#if defined(CONFIG_ARCH_SUN8IW7P1)
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#define SUNXI_SPI0_BASE (0x01c68000L)
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#elif defined(CONFIG_ARCH_SUN8IW11P1)
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#define SUNXI_SPI0_BASE (0x01c05000L)
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#endif
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#if defined(CONFIG_ARCH_SUN8IW7P1)
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#define SUNXI_SPI1_BASE (0x01c69000L)
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#elif defined(CONFIG_ARCH_SUN8IW11P1)
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#define SUNXI_SPI1_BASE (0x01c69000L)
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#endif
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#define SUNXI_GMAC_BASE (0x01c50000L)
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//todo:#define SUNXI_GPADC_BASE (0x05070000L)
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#define SUNXI_LRADC_BASE (0X01C21800L)
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#define SUNXI_KEYADC_BASE SUNXI_LRADC_BASE
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#if defined(CONFIG_ARCH_SUN8IW7P1)
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#define SUNXI_USBOTG_BASE (0x01c19000L)
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#elif defined(CONFIG_ARCH_SUN8IW11P1)
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#define SUNXI_USBOTG_BASE (0x01c13000L)
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#endif
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#if defined(CONFIG_ARCH_SUN8IW7P1)
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#define SUNXI_EHCI0_BASE (0x01c1a000L)
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#elif defined(CONFIG_ARCH_SUN8IW11P1)
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#define SUNXI_EHCI0_BASE (0x01c14000L)
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#endif
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#if defined(CONFIG_ARCH_SUN8IW7P1)
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#define SUNXI_EHCI1_BASE (0x01c1b000L)
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#elif defined(CONFIG_ARCH_SUN8IW11P1)
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#define SUNXI_EHCI1_BASE (0x01c19000L)
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#endif
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#if defined(CONFIG_ARCH_SUN8IW7P1)
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#define SUNXI_WDOG_BASE (0x01C20CA0L)
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#elif defined(CONFIG_ARCH_SUN8IW11P1)
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#define SUNXI_WDOG_BASE (0x01C20C90L)
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#endif
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//todo:#define ARMV7_GIC_BASE (SUNXI_GIC_BASE+0x1000L)
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//todo:#define ARMV7_CPUIF_BASE (SUNXI_GIC_BASE+0x2000L)
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//cpus
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#if defined(CONFIG_ARCH_SUN8IW7P1) || defined(CONFIG_ARCH_SUN8IW21P1)
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#define SUNXI_RTC_BASE (0x01f00000L)
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#elif defined(CONFIG_ARCH_SUN8IW11P1)
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#define SUNXI_RTC_BASE (0x01c20400L)
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#endif
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#if defined(CONFIG_ARCH_SUN8IW7P1)
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#define SUNXI_CPUS_CFG_BASE (0x01f01C00L)
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#elif defined(CONFIG_ARCH_SUN8IW11P1)
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#define SUNXI_CPUS_CFG_BASE (0x01c25C00L)
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#endif
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#define SUNXI_RCPUCFG_BASE (SUNXI_CPUS_CFG_BASE)
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#define SUNXI_RPRCM_BASE (0x01f01400L)
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#define SUNXI_RTWI_BRG_REG (SUNXI_RPRCM_BASE + 0x019c)
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//todo:#define SUNXI_RPWM_BASE (0x07020c00L)
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//#define SUNXI_RPIO_BASE (0X01F02C00L)
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#define SUNXI_R_PIO_BASE (0X01F02C00L)
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//todo:#define SUNXI_RTWI_BASE (0x07081400L)
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//todo:#define SUNXI_RRSB_BASE (0x07083000L)
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//todo:#define SUNXI_RSB_BASE (0x07083000L)
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#define SUNXI_RTC_DATA_BASE (SUNXI_RTC_BASE + 0x100)
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/* use for usb correct */
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//todo:#ifdef CONFIG_ARCH_SUN8IW18P1
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//todo:#define VDD_SYS_PWROFF_GATING_REG (SUNXI_RTC_BASE + 0x220)
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//todo:#define RES_CAL_CTRL_REG (SUNXI_RTC_BASE + 0X230)
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//todo:#else
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//todo:#define VDD_SYS_PWROFF_GATING_REG (SUNXI_RPRCM_BASE + 0x250)
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//todo:#define RES_CAL_CTRL_REG (SUNXI_RPRCM_BASE + 0X310)
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//todo:#define VDD_ADDA_OFF_GATING (9)
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//todo:#define CAL_ANA_EN (1)
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//todo:#define CAL_EN (0)
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//todo:#endif
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//todo:#define RVBARADDR0_L (SUNXI_CPUXCFG_BASE+0x40)
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//todo:#define RVBARADDR0_H (SUNXI_CPUXCFG_BASE+0x44)
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//todo:#define SRAM_CONTRL_REG0 (SUNXI_SYSCRL_BASE+0x0)
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//todo:#define SRAM_CONTRL_REG1 (SUNXI_SYSCRL_BASE+0x4)
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//todo:#define GPIO_BIAS_MAX_LEN (32)
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//todo:#define GPIO_BIAS_MAIN_NAME "gpio_bias"
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//todo:#define GPIO_POW_MODE_REG (0x0340)
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//todo:#define GPIO_3_3V_MODE 0
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//todo:#define GPIO_1_8V_MODE 1
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#endif
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