202 lines
6.0 KiB
C
202 lines
6.0 KiB
C
/*
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* (C) Copyright 2015 Roy Spliet <rspliet@ultimaker.com>
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*/
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#ifndef _SUNXI_DMA_H
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#define _SUNXI_DMA_H
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#define SUNXI_DMA_CHANNAL_BASE (SUNXI_DMA_BASE + 0x100)
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#define DMA_AUTO_GATE_REG (SUNXI_DMA_BASE + 0x28)
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#define SUNXI_DMA_CHANANL_SIZE (0x40)
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#define SUNXI_DMA_LINK_NULL (0xfffff800)
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#define DMAC_DMATYPE_NORMAL 0
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#define DMAC_CFG_TYPE_DRAM (1)
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#define DMAC_CFG_TYPE_SRAM (0)
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#if defined(CONFIG_ARCH_SUN8IW18) ||\
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defined(CONFIG_ARCH_SUN50IW9) ||\
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defined(CONFIG_ARCH_SUN50IW10) ||\
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defined(CONFIG_ARCH_SUN8IW19) ||\
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defined(CONFIG_ARCH_SUN8IW20) ||\
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defined(CONFIG_ARCH_SUN8IW21) ||\
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defined(CONFIG_ARCH_SUN20IW1P1) || \
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defined(CONFIG_ARCH_SUN50IW5)
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#define DMAC_CFG_TYPE_SPI0 (22)
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#define DMAC_CFG_SRC_TYPE_NAND (5)
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#elif defined(CONFIG_ARCH_SUN8IW15)
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#define DMAC_CFG_TYPE_SPI0 (23)
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#define DMAC_CFG_SRC_TYPE_NAND (5)
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#elif defined(CONFIG_ARCH_SUN8IW7) || defined(CONFIG_ARCH_SUN8IW11)
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#define DMAC_CFG_TYPE_SPI0 (24)
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#define DMAC_CFG_SRC_TYPE_NAND (5)
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#elif defined(CONFIG_ARCH_SUN50IW11) || defined(CONFIG_ARCH_SUN55IW3)
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#define DMAC_CFG_TYPE_SPI0 (22)
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#define DMAC_CFG_SRC_TYPE_NAND (10)
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#endif
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/* DMA base config */
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#define DMAC_CFG_CONTINUOUS_ENABLE (0x01)
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#define DMAC_CFG_CONTINUOUS_DISABLE (0x00)
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/* ----------DMA dest config-------------------- */
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/* DMA dest width config */
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#define DMAC_CFG_DEST_DATA_WIDTH_8BIT (0x00)
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#define DMAC_CFG_DEST_DATA_WIDTH_16BIT (0x01)
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#define DMAC_CFG_DEST_DATA_WIDTH_32BIT (0x02)
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/* DMA dest bust config */
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#define DMAC_CFG_DEST_1_BURST (0x00)
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#define DMAC_CFG_DEST_4_BURST (0x01)
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#define DMAC_CFG_DEST_8_BURST (0x02)
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#define DMAC_CFG_DEST_ADDR_TYPE_LINEAR_MODE (0x00)
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#define DMAC_CFG_DEST_ADDR_TYPE_IO_MODE (0x01)
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/* ----------DMA src config -------------------*/
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#define DMAC_CFG_SRC_DATA_WIDTH_8BIT (0x00)
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#define DMAC_CFG_SRC_DATA_WIDTH_16BIT (0x01)
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#define DMAC_CFG_SRC_DATA_WIDTH_32BIT (0x02)
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#define DMAC_CFG_SRC_1_BURST (0x00)
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#define DMAC_CFG_SRC_4_BURST (0x01)
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#define DMAC_CFG_SRC_8_BURST (0x02)
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#define DMAC_CFG_SRC_ADDR_TYPE_LINEAR_MODE (0x00)
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#define DMAC_CFG_SRC_ADDR_TYPE_IO_MODE (0x01)
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/*dma int config*/
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#define DMA_PKG_HALF_INT (1 << 0)
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#define DMA_PKG_END_INT (1 << 1)
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#define DMA_QUEUE_END_INT (1 << 2)
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typedef struct {
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unsigned int config;
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unsigned int source_addr;
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unsigned int dest_addr;
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unsigned int byte_count;
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unsigned int commit_para;
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unsigned int link;
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unsigned int reserved[2];
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} sunxi_dma_desc;
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#if defined(CONFIG_ARCH_SUN50IW3) || defined(CONFIG_ARCH_SUN8IW18) || \
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defined(CONFIG_ARCH_SUN50IW9) || defined(CONFIG_ARCH_SUN8IW16) || \
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defined(CONFIG_ARCH_SUN8IW19) || defined(CONFIG_ARCH_SUN50IW10) || \
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defined(CONFIG_ARCH_SUN8IW15) || defined(CONFIG_ARCH_SUN8IW7) || \
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defined(CONFIG_ARCH_SUN50IW11) || defined(CONFIG_ARCH_SUN50IW12) || \
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defined(CONFIG_ARCH_SUN8IW20) || defined(CONFIG_ARCH_SUN20IW1P1) || \
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defined(CONFIG_ARCH_SUN50IW5) || defined(CONFIG_ARCH_SUN55IW3) || \
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defined(CONFIG_ARCH_SUN8IW21)
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typedef struct {
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unsigned int src_drq_type : 6;
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unsigned int src_burst_length : 2;
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unsigned int src_addr_mode : 1;
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unsigned int src_data_width : 2;
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unsigned int reserved0 : 5;
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unsigned int dst_drq_type : 6;
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unsigned int dst_burst_length : 2;
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unsigned int dst_addr_mode : 1;
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unsigned int dst_data_width : 2;
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unsigned int reserved1 : 5;
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} sunxi_dma_channal_config;
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#elif defined(CONFIG_ARCH_SUN8IW11)
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typedef struct {
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unsigned int src_drq_type : 5;
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unsigned int src_addr_mode : 2;
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unsigned int src_burst_length : 2;
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unsigned int src_data_width : 2;
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unsigned int reserved0 : 5;
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unsigned int dst_drq_type : 5;
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unsigned int dst_addr_mode : 2;
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unsigned int dst_burst_length : 2;
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unsigned int dst_data_width : 2;
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unsigned int reserved1 : 5;
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} sunxi_dma_channal_config;
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#else
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#error "DMA definition not available for this architecture"
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#endif
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typedef struct {
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sunxi_dma_channal_config channal_cfg;
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unsigned int loop_mode;
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unsigned int data_block_size;
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unsigned int wait_cyc;
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} sunxi_dma_set;
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struct dma_irq_handler {
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void *m_data;
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void (*m_func)(void *data);
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};
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typedef struct {
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unsigned int enable;
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unsigned int pause;
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unsigned int desc_addr;
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unsigned int config;
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unsigned int cur_src_addr;
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unsigned int cur_dst_addr;
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unsigned int left_bytes;
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unsigned int parameters;
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unsigned int mode;
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unsigned int fdesc_addr;
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unsigned int pkg_num;
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unsigned int res[5];
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} sunxi_dma_channal_reg;
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typedef struct {
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unsigned int irq_en0; /* 0x0 dma irq enable register 0 */
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unsigned int irq_en1; /* 0x4 dma irq enable register 1 */
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unsigned int reserved0[2];
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unsigned int irq_pending0; /* 0x10 dma irq pending register 0 */
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unsigned int irq_pending1; /* 0x14 dma irq pending register 1 */
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unsigned int reserved1[2];
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unsigned int security; /* 0x20 dma security register */
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unsigned int reserved3[1];
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unsigned int auto_gate; /* 0x28 dma auto gating register */
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unsigned int reserved4[1];
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unsigned int status; /* 0x30 dma status register */
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unsigned int reserved5[3];
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unsigned int version; /* 0x40 dma Version register */
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unsigned int reserved6[47];
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sunxi_dma_channal_reg channal[16]; /* 0x100 dma channal register */
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} sunxi_dma_reg;
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typedef struct sunxi_dma_source_t {
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unsigned int used;
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unsigned int channal_count;
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sunxi_dma_channal_reg *channal;
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unsigned int reserved;
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sunxi_dma_desc *desc;
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struct dma_irq_handler dma_func;
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} sunxi_dma_source;
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#define DMA_RST_OFS 16
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#define DMA_GATING_OFS 0
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extern void sunxi_dma_init(void);
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extern void sunxi_dma_exit(void);
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extern ulong sunxi_dma_request(unsigned int dmatype);
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extern ulong sunxi_dma_request_from_last(unsigned int dmatype);
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extern int sunxi_dma_release(unsigned long hdma);
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extern int sunxi_dma_setting(unsigned long hdma, sunxi_dma_set *cfg);
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extern int sunxi_dma_start(unsigned long hdma, phys_addr_t saddr, phys_addr_t daddr,
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unsigned int bytes);
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extern int sunxi_dma_stop(unsigned long hdma);
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extern int sunxi_dma_querystatus(unsigned long hdma);
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extern int sunxi_dma_install_int(ulong hdma, void *p);
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extern int sunxi_dma_disable_int(ulong hdma);
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extern int sunxi_dma_enable_int(ulong hdma);
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extern int sunxi_dma_free_int(ulong hdma);
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#endif /* _SUNXI_DMA_H */
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