91 lines
4.4 KiB
C
91 lines
4.4 KiB
C
#ifndef _SUNXI_GPIO_NEW_H
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#define _SUNXI_GPIO_NEW_H
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#include <arch/gpio.h>
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#ifdef CFG_SET_BACKLIGHT
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#define CFG_SET_GPIO_NEW 1
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#endif
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#define OUPUT_HIGH_LEVEL (1)
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#define OUPUT_LOW_LEVEL (0)
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#define PORT_NO_USE (0xFF)
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#define PORT_NUM_NO_USE (0xFF)
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/**#############################################################################################################
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*
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* GPIO(PIN) NEW Operations
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*
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-##############################################################################################################*/
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#define NEW_PIO_REG_CFG(n, i) \
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((volatile unsigned int *)((phys_addr_t)SUNXI_PIO_BASE + \
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(n)*PIOC_o_OFFSET + ((i) << 2) + \
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PIOC_REG_o_CFG0))
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#define NEW_PIO_REG_DLEVEL(n, i) \
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((volatile unsigned int *)((phys_addr_t)SUNXI_PIO_BASE + \
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(n)*PIOC_o_OFFSET + ((i) << 2) + \
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PIOC_REG_o_DRV0))
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#define NEW_PIO_REG_PULL(n, i) \
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((volatile unsigned int *)((phys_addr_t)SUNXI_PIO_BASE + \
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(n)*PIOC_o_OFFSET + ((i) << 2) + \
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PIOC_REG_o_PUL0))
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#define NEW_PIO_REG_DATA(n) \
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((volatile unsigned int *)((phys_addr_t)SUNXI_PIO_BASE + \
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(n)*PIOC_o_OFFSET + PIOC_REG_o_DATA))
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#define NEW_PIO_ONE_PIN_DATA(n, i) \
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(((*(volatile unsigned int *)((phys_addr_t)SUNXI_PIO_BASE + \
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(n) * PIOC_o_OFFSET + \
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PIOC_REG_o_DATA)) & \
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(1 << i)) >> \
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i)
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#define NEW_PIO_REG_CFG_VALUE(n, i) \
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readl(SUNXI_PIO_BASE + (n)*PIOC_o_OFFSET + ((i) << 2) + PIOC_REG_o_CFG0)
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#define NEW_PIO_REG_DLEVEL_VALUE(n, i) \
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readl(SUNXI_PIO_BASE + (n)*PIOC_o_OFFSET + ((i) << 2) + PIOC_REG_o_DRV0)
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#define NEW_PIO_REG_PULL_VALUE(n, i) \
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readl(SUNXI_PIO_BASE + (n)*PIOC_o_OFFSET + ((i) << 2) + PIOC_REG_o_PUL0)
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#define NEW_PIO_REG_DATA_VALUE(n) \
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readl(SUNXI_PIO_BASE + (n)*PIOC_o_OFFSET + PIOC_REG_o_DATA)
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#define NEW_PIO_REG_BASE(n) \
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((volatile unsigned int *)((phys_addr_t)SUNXI_PIO_BASE + \
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(n)*PIOC_o_OFFSET))
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#ifdef SUNXI_R_PIO_BASE
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#define R_NEW_PIO_REG_CFG(n, i) \
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((volatile unsigned int *)((phys_addr_t)SUNXI_R_PIO_BASE + \
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((n)-11) * PIOC_o_OFFSET + ((i) << 2) + \
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PIOC_REG_o_CFG0))
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#define R_NEW_PIO_REG_DLEVEL(n, i) \
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((volatile unsigned int *)((phys_addr_t)SUNXI_R_PIO_BASE + \
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((n)-11) * PIOC_o_OFFSET + ((i) << 2) + \
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PIOC_REG_o_DRV0))
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#define R_NEW_PIO_REG_PULL(n, i) \
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((volatile unsigned int *)((phys_addr_t)SUNXI_R_PIO_BASE + \
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((n)-11) * PIOC_o_OFFSET + ((i) << 2) + \
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PIOC_REG_o_PUL0))
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#define R_NEW_PIO_REG_DATA(n) \
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((volatile unsigned int *)((phys_addr_t)SUNXI_R_PIO_BASE + \
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((n)-11) * PIOC_o_OFFSET + \
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PIOC_REG_o_DATA))
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#define R_NEW_PIO_REG_CFG_VALUE(n, i) \
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readl(SUNXI_R_PIO_BASE + ((n)-11) * PIOC_o_OFFSET + ((i) << 2) + \
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PIOC_REG_o_CFG0)
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#define R_NEW_PIO_REG_DLEVEL_VALUE(n, i) \
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readl(SUNXI_R_PIO_BASE + ((n)-11) * PIOC_o_OFFSET + ((i) << 2) + \
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PIOC_REG_o_DRV0)
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#define R_NEW_PIO_REG_PULL_VALUE(n, i) \
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readl(SUNXI_R_PIO_BASE + ((n)-11) * PIOC_o_OFFSET + ((i) << 2) + \
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PIOC_REG_o_PUL0)
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#define R_NEW_PIO_REG_DATA_VALUE(n) \
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readl(SUNXI_R_PIO_BASE + ((n)-11) * PIOC_o_OFFSET + PIOC_REG_o_DATA)
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#define R_NEW_PIO_REG_BASE(n) \
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((volatile unsigned int *)((phys_addr_t)SUNXI_R_PIO_BASE + \
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((n)-11) * PIOC_o_OFFSET))
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#endif
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#ifdef CFG_SET_GPIO_NEW
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int boot_set_gpio_new(void *user_gpio_list, u32 group_count_max, int set_gpio);
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#endif
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#endif |