77 lines
3.0 KiB
C
77 lines
3.0 KiB
C
/*
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* (C) Copyright 2018
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* wangwei <wangwei@allwinnertech.com>
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*/
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#ifndef _SUN20IW1_H
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#define _SUN20IW1_H
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#define BOOT_PUB_HEAD_VERSION "3000"
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#define CONFIG_ARCH_SUN20IW1
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#define CONFIG_ARCH_SUN20IW1P1
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#define CONFIG_RISCV
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#define CONFIG_SUNXI_NCAT_V2
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#define CONFIG_SUNXI_GPIO_V2
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#define CONFIG_DRAM_PARA_V1
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/* #define FPGA_PLATFORM */
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/* sram layout*/
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#define CONFIG_SYS_SRAM_BASE (0x20000)
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#define CONFIG_SYS_SRAM_SIZE (0x8000)
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#define CONFIG_SYS_SRAMA2_BASE (0x100000)
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#define CONFIG_SYS_SRAMA2_SIZE (0x1C000)
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#define CONFIG_SYS_SRAMC_BASE (0x28000)
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#define CONFIG_SYS_SRAMC_SIZE (128 << 10)
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/* dram layout*/
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#define SDRAM_OFFSET(x) ((phys_addr_t)0x40000000 + (x))
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#define CONFIG_SYS_DRAM_BASE SDRAM_OFFSET(0)
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#define DRAM_PARA_STORE_ADDR SDRAM_OFFSET(0x00800000) /*fel*/ /*same as base.h*/
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#define CONFIG_HEAP_BASE SDRAM_OFFSET(0x00800000) /*secure */ /*same as base.h*/
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#define CONFIG_HEAP_SIZE (16 * 1024 * 1024) /*same as base.h*/
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#define CONFIG_BOOTPKG_BASE SDRAM_OFFSET(0x01000000) /*same as base.h*/
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#define SUNXI_DRAM_PARA_MAX 32
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/*same as base.h*/
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#define SUNXI_LOGO_COMPRESSED_LOGO_SIZE_ADDR SDRAM_OFFSET(0x03000000)
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#define SUNXI_LOGO_COMPRESSED_LOGO_BUFF SDRAM_OFFSET(0x03000010)
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#define SUNXI_SHUTDOWN_CHARGE_COMPRESSED_LOGO_SIZE_ADDR SDRAM_OFFSET(0x03100000)
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#define SUNXI_SHUTDOWN_CHARGE_COMPRESSED_LOGO_BUFF SDRAM_OFFSET(0x03100010)
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#define SUNXI_ANDROID_CHARGE_COMPRESSED_LOGO_SIZE_ADDR SDRAM_OFFSET(0x03200000)
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#define SUNXI_ANDROID_CHARGE_COMPRESSED_LOGO_BUFF SDRAM_OFFSET(0x03200010)
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/* boot run addr */
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#define FEL_BASE 0x20
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#define SECURE_FEL_BASE (0x20)
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#define CONFIG_BOOT0_RUN_ADDR (0x20000) /* sram a */
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#define CONFIG_NBOOT_STACK (CONFIG_SYS_SRAMC_BASE+CONFIG_SYS_SRAMC_SIZE)
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#define CONFIG_TOC0_RUN_ADDR (0x20480) /* sram a */
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#define CONFIG_HASH_TABLE_STACK_GAP (4)
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#define CONFIG_HASH_INFO_TABLE_SIZE (512 - CONFIG_HASH_TABLE_STACK_GAP)/*to pass hash info to optee*/
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#define CONFIG_HASH_INFO_TABLE_BASE (CONFIG_SYS_SRAMC_BASE + CONFIG_SYS_SRAMC_SIZE - CONFIG_HASH_INFO_TABLE_SIZE)
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#define CONFIG_SBOOT_STACK (CONFIG_HASH_INFO_TABLE_BASE - CONFIG_HASH_TABLE_STACK_GAP)
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#define CONFIG_BOOT0_RET_ADDR (CONFIG_SYS_SRAM_BASE)
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#define CONFIG_TOC0_HEAD_BASE (CONFIG_SYS_SRAM_BASE)
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#define CONFIG_TOC0_CFG_ADDR (CONFIG_SYS_SRAM_BASE + 0x80)
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#define CONFIG_SYS_INIT_RAM_SIZE (CONFIG_SYS_SRAM_SIZE)
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/* FES */
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#define CONFIG_FES1_RUN_ADDR (0x28000)
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#define CONFIG_FES1_RET_ADDR (CONFIG_SYS_SRAMC_BASE + 0x7210)
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/*CPU vol for boot*/
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#define CONFIG_SUNXI_CORE_VOL 900
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/*sys vol for boot*/
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#define CONFIG_SUNXI_SYS_VOL 900
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/* watchdog */
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#define WDOG_TIMEOUT 16
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#endif
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