89 lines
3.6 KiB
C
89 lines
3.6 KiB
C
/*
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* (C) Copyright 2013-2019
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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*
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*/
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#ifndef _SUN55IW3_H
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#define _SUN55IW3_H
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#define FPGA_PLATFORM
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#define BOOT_PUB_HEAD_VERSION "3000"
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#define CONFIG_ARCH_SUN55IW3
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#define CONFIG_ARCH_SUN55IW3P1
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#define CONFIG_DRAM_PARA_V1
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#define CONFIG_MONITOR
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#define CONFIG_SUNXI_VERSION_AOTUGEN 1
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/*#define FPGA_PLATFORM*/
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/* sram layout*/
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#define CONFIG_SYS_SRAM_BASE (0x20000)
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#define CONFIG_SYS_SRAM_SIZE (0x10000)
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#define CONFIG_SYS_SRAMA2_BASE (0x40000) /*(SUNXI_SRAM_A2_BASE)*/
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#define CONFIG_SYS_SRAMA2_SIZE (0x24000)
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#define CONFIG_SYS_SRAMC_BASE (CONFIG_SYS_SRAMA2_BASE+0x10000)
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#define CONFIG_SYS_SRAMC_SIZE (0x5000)
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/* dram layout*/
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#define SDRAM_OFFSET(x) (0x40000000+(x))
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#define CONFIG_SYS_DRAM_BASE SDRAM_OFFSET(0)
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#define DRAM_PARA_STORE_ADDR SDRAM_OFFSET(0x00800000) /*fel*/
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#define CONFIG_HEAP_BASE SDRAM_OFFSET(0x00800000) /*secure */
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#define CONFIG_HEAP_SIZE (16 * 1024 * 1024)
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#define CONFIG_BOOTPKG_BASE SDRAM_OFFSET(0x02e00000)
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#define CONFIG_MONITOR_BASE SDRAM_OFFSET(0x08000000)
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#define SCP_DRAM_BASE SDRAM_OFFSET(0x08100000)
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#define SCP_DTS_BASE SDRAM_OFFSET(0x08100000)
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#define SUNXI_DRAM_PARA_MAX 32
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#define SUNXI_LOGO_COMPRESSED_LOGO_SIZE_ADDR SDRAM_OFFSET(0x03000000)
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#define SUNXI_LOGO_COMPRESSED_LOGO_BUFF SDRAM_OFFSET(0x03000010)
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#define SUNXI_SHUTDOWN_CHARGE_COMPRESSED_LOGO_SIZE_ADDR SDRAM_OFFSET(0x03100000)
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#define SUNXI_SHUTDOWN_CHARGE_COMPRESSED_LOGO_BUFF SDRAM_OFFSET(0x03100010)
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#define SUNXI_ANDROID_CHARGE_COMPRESSED_LOGO_SIZE_ADDR SDRAM_OFFSET(0x03200000)
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#define SUNXI_ANDROID_CHARGE_COMPRESSED_LOGO_BUFF SDRAM_OFFSET(0x03200010)
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/* scp mem layout */
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#define SCP_DRAM_SIZE (0x0000) /* no cpus dram code on sun50iw10 */
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#define SCP_DTS_SIZE (0x40000)
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#define SCP_CODE_DRAM_OFFSET (0x14000)
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#define SCP_SRAM_BASE (CONFIG_SYS_SRAMA2_BASE)
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#define SCP_SRAM_SIZE (CONFIG_SYS_SRAMA2_SIZE)
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#define HEADER_OFFSET (0x4000)
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/*dram_para_offset is the numbers of u32 before dram data sturcture(dram_para) in struct arisc_para*/
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#define SCP_DRAM_PARA_OFFSET (sizeof(u32) * 2)
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#define SCP_DARM_PARA_NUM (32)
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/* boot run addr */
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#define FEL_BASE 0x20
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#define SECURE_FEL_BASE (0x64)
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#define CONFIG_BOOT0_RUN_ADDR (0x44000) /* sram a */
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#define CONFIG_NBOOT_STACK (CONFIG_SYS_SRAMA2_BASE+CONFIG_SYS_SRAMA2_SIZE)
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#define CONFIG_TOC0_RUN_ADDR (0x20480) /* sram a */
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#define CONFIG_HASH_TABLE_STACK_GAP (4)
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#define CONFIG_HASH_INFO_TABLE_SIZE (512 - CONFIG_HASH_TABLE_STACK_GAP)/*to pass hash info to optee*/
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#define CONFIG_HASH_INFO_TABLE_BASE (CONFIG_SYS_SRAMC_BASE + CONFIG_SYS_SRAMC_SIZE - CONFIG_HASH_INFO_TABLE_SIZE)
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#define CONFIG_SBOOT_STACK (CONFIG_HASH_INFO_TABLE_BASE - CONFIG_HASH_TABLE_STACK_GAP)
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#define CONFIG_BOOT0_RET_ADDR (CONFIG_SYS_SRAMC_BASE)
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#define CONFIG_TOC0_HEAD_BASE (CONFIG_SYS_SRAMC_BASE)
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#define CONFIG_TOC0_CFG_ADDR (CONFIG_SYS_SRAMC_BASE + 0x80)
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#define CONFIG_SYS_INIT_RAM_SIZE 0x8000
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/* FES */
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#define CONFIG_FES1_RUN_ADDR (0x28000)
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#define CONFIG_FES1_RET_ADDR (CONFIG_SYS_SRAMC_BASE + 0x7210)
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/*CPU vol for boot*/
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#define CONFIG_SUNXI_CORE_VOL 1100
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#define CONFIG_SUNXI_SYS_VOL 950
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/*R_GPIO: PL0,PL1 cfg*/
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#define PL_CTL_REG0 (0x22)
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#endif
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