80 lines
2.9 KiB
C
80 lines
2.9 KiB
C
/*
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* (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
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*
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* Configuration settings for the Allwinner A80 (sun9i) CPU
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*/
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#ifndef _SUN8IW11_H
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#define _SUN8IW11_H
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#define BOOT_PUB_HEAD_VERSION "3000"
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#define CONFIG_ARCH_SUN8IW11
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#define CONFIG_ARCH_SUN8IW11P1
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#define CONFIG_SUNXI_VERSION1
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#define CONFIG_DRAM_PARA_V1
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/* sram layout*/
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#define CONFIG_SYS_SRAM_BASE (0x0)
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#define CONFIG_SYS_SRAM_SIZE (0x8000)
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#define CONFIG_SYS_SRAMA3_BASE (0x8000)
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#define CONFIG_SYS_SRAMA3_SIZE (0x3400)
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#define CONFIG_SYS_SRAMA4_BASE (0xB400)
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#define CONFIG_SYS_SRAMA4_SIZE (0x0C00)
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#define CONFIG_SYS_SRAMD_BASE (0x10000)
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#define CONFIG_SYS_SRAMD_SIZE (0x1000)
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#define SCP_SRAM_BASE (0x40000)
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#define SCP_SRAM_SIZE (0xC000)
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#define SCP_DRAM_BASE (0x43080000)
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#define SCP_DRAM_SIZE (0x10000)
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#define SCP_CODE_DRAM_OFFSET (0xC000)
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#define HEADER_OFFSET (0x4000)
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/*dram_para_offset is the numbers of u32 before dram data sturcture(dram_para) in struct arisc_para*/
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#define SCP_DRAM_PARA_OFFSET (sizeof(u32) * 2)
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#define SCP_DARM_PARA_NUM (0)
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/* dram layout*/
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#define SDRAM_OFFSET(x) (0x40000000 + (x))
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#define CONFIG_SYS_DRAM_BASE SDRAM_OFFSET(0)
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#define DRAM_PARA_STORE_ADDR SDRAM_OFFSET(0x00800000) /*fel*/
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#define CONFIG_HEAP_BASE SDRAM_OFFSET(0x00800000) /*secure */
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#define CONFIG_HEAP_SIZE (16 * 1024 * 1024)
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#define CONFIG_BOOTPKG_BASE SDRAM_OFFSET(0x02e00000)
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#define CONFIG_MONITOR_BASE SDRAM_OFFSET(0x08000000)
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#define SUNXI_DRAM_PARA_MAX 32
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#define SUNXI_LOGO_COMPRESSED_LOGO_SIZE_ADDR SDRAM_OFFSET(0x03000000)
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#define SUNXI_LOGO_COMPRESSED_LOGO_BUFF SDRAM_OFFSET(0x03000010)
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#define SUNXI_SHUTDOWN_CHARGE_COMPRESSED_LOGO_SIZE_ADDR SDRAM_OFFSET(0x03100000)
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#define SUNXI_SHUTDOWN_CHARGE_COMPRESSED_LOGO_BUFF SDRAM_OFFSET(0x03100010)
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#define SUNXI_ANDROID_CHARGE_COMPRESSED_LOGO_SIZE_ADDR SDRAM_OFFSET(0x03200000)
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#define SUNXI_ANDROID_CHARGE_COMPRESSED_LOGO_BUFF SDRAM_OFFSET(0x03200010)
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/* boot run addr */
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#define FEL_BASE 0xffff0020
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#define SECURE_FEL_BASE (0xffff0064)
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#define CONFIG_BOOT0_RUN_ADDR (CONFIG_SYS_SRAM_BASE) /* sram a */
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#define CONFIG_NBOOT_STACK (CONFIG_SYS_SRAMD_BASE + CONFIG_SYS_SRAMD_SIZE - 4)
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#define CONFIG_TOC0_RUN_ADDR (CONFIG_SYS_SRAM_BASE + 0x480) /* sram a */
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#define CONFIG_SBOOT_STACK \
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(CONFIG_SYS_SRAMD_BASE + CONFIG_SYS_SRAMD_SIZE - 4)
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#
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#define CONFIG_BOOT0_RET_ADDR (CONFIG_SYS_SRAM_BASE)
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#define CONFIG_TOC0_HEAD_BASE (CONFIG_SYS_SRAM_BASE)
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#define CONFIG_TOC0_CFG_ADDR (CONFIG_SYS_SRAM_BASE + 0x80)
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#define CONFIG_SYS_INIT_RAM_SIZE (CONFIG_SYS_SRAM_SIZE)
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/* FES */
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#define CONFIG_FES1_RUN_ADDR (0x7000)
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#define CONFIG_FES1_RET_ADDR (CONFIG_SYS_SRAM_BASE + 0x7210)
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/*CPU vol for boot*/
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#define CONFIG_SUNXI_CORE_VOL 900
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#endif
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