492 lines
9.6 KiB
C
492 lines
9.6 KiB
C
/*
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* ac107.h -- ac107 ALSA Soc Audio driver
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*
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* Version: 1.0
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*
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* Author: panjunwen
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#ifndef _AC107_H
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#define _AC107_H
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/*** AC107 Codec Register Define***/
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//Chip Reset
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#define CHIP_AUDIO_RST 0x00
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//Power Control
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#define PWR_CTRL1 0x01
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#define PWR_CTRL2 0x02
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//PLL Configure Control
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#define PLL_CTRL1 0x10
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#define PLL_CTRL2 0x11
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#define PLL_CTRL3 0x12
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#define PLL_CTRL4 0x13
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#define PLL_CTRL5 0x14
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#define PLL_CTRL6 0x16
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#define PLL_CTRL7 0x17
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#define PLL_LOCK_CTRL 0x18
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//System Clock Control
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#define SYSCLK_CTRL 0x20
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#define MOD_CLK_EN 0x21
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#define MOD_RST_CTRL 0x22
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//I2S Common Control
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#define I2S_CTRL 0x30
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#define I2S_BCLK_CTRL 0x31
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#define I2S_LRCK_CTRL1 0x32
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#define I2S_LRCK_CTRL2 0x33
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#define I2S_FMT_CTRL1 0x34
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#define I2S_FMT_CTRL2 0x35
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#define I2S_FMT_CTRL3 0x36
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//I2S TX Control
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#define I2S_TX_CTRL1 0x38
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#define I2S_TX_CTRL2 0x39
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#define I2S_TX_CTRL3 0x3A
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#define I2S_TX_CHMP_CTRL1 0x3C
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#define I2S_TX_CHMP_CTRL2 0x3D
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//I2S RX Control
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#define I2S_RX_CTRL1 0x50
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#define I2S_RX_CTRL2 0x51
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#define I2S_RX_CTRL3 0x52
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#define I2S_RX_CHMP_CTRL1 0x54
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#define I2S_RX_CHMP_CTRL2 0x55
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//PDM Control
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#define PDM_CTRL 0x59
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//ADC Common Control
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#define ADC_SPRC 0x60
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#define ADC_DIG_EN 0x61
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#define DMIC_EN 0x62
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#define HPF_EN 0x66
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//ADC Digital Channel Volume Control
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#define ADC1_DVOL_CTRL 0x70
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#define ADC2_DVOL_CTRL 0x71
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//ADC Digital Mixer Source and Gain Control
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#define ADC1_DMIX_SRC 0x76
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#define ADC2_DMIX_SRC 0x77
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//ADC Digital Debug Control
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#define ADC_DIG_DEBUG 0x7F
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//IO Function and Drive Control
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#define ADC_ANA_DEBUG1 0x80
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#define ADC_ANA_DEBUG2 0x81
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#define I2S_PADDRV_CTRL 0x82
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//ADC1 Analog Control
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#define ANA_ADC1_CTRL1 0xA0
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#define ANA_ADC1_CTRL2 0xA1
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#define ANA_ADC1_CTRL3 0xA2
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#define ANA_ADC1_CTRL4 0xA3
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#define ANA_ADC1_CTRL5 0xA4
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//ADC2 Analog Control
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#define ANA_ADC2_CTRL1 0xA5
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#define ANA_ADC2_CTRL2 0xA6
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#define ANA_ADC2_CTRL3 0xA7
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#define ANA_ADC2_CTRL4 0xA8
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#define ANA_ADC2_CTRL5 0xA9
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//ADC Dither Control
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#define ADC_DITHER_CTRL 0xAA
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/*** AC107 Codec Register Bit Define***/
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/* PWR_CTRL1 */
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#define VREF_ENABLE 7
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#define VREF_LPMODE 6
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#define VREF_FSU_DISABLE 5
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#define VREF_RESCTRL 3
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#define IGEN_TRIM 0
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/* PWR_CTRL2 */
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#define VREF_SEL 7
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#define MICBIAS2_EN 6
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#define MICBIAS2_VCTRL 4
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#define MICBIAS1_EN 2
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#define MICBIAS1_VCTRL 0
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/*PLL_CTRL1*/
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#define PLL_IBIAS 4
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#define PLL_NDET 3
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#define PLL_LOCKED_STATUS 2
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#define PLL_COM_EN 1
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#define PLL_EN 0
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/*PLL_CTRL2*/
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#define PLL_PREDIV2 5
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#define PLL_PREDIV1 0
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/*PLL_CTRL3*/
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#define PLL_LOOPDIV_MSB 0
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/*PLL_CTRL4*/
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#define PLL_LOOPDIV_LSB 0
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/*PLL_CTRL5*/
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#define PLL_POSTDIV2 5
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#define PLL_POSTDIV1 0
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/*PLL_CTRL6*/
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#define PLL_LDO 6
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#define PLL_CP 0
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/*PLL_CTRL7*/
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#define PLL_CAP 6
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#define PLL_RES 4
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/*PLL_LOCK_CTRL*/
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#define SYSCLK_HOLD_TIME 4
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#define LOCK_LEVEL1 2
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#define LOCK_LEVEL2 1
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#define PLL_LOCK_EN 0
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/* SYSCLK_CTRL */
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#define PLLCLK_EN 7
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#define PLLCLK_SRC 4
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#define SYSCLK_SRC 2
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#define SYSCLK_EN 0
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/* MOD_CLK_EN & MOD_RST_CTRL */
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#define I2S_RST 4
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#define ADC_ANALOG 2
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#define ADC_DIGITAL 1
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#define I2S 0
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/* I2S_CTRL */
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#define BCLK_IOEN 7
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#define LRCK_IOEN 6
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#define MCLK_IOEN 5
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#define SDO_EN 4
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#define TXEN 2
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#define RXEN 1
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#define GEN 0
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/* I2S_BCLK_CTRL */
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#define EDGE_TRANSFER 5
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#define BCLK_POLARITY 4
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#define BCLKDIV 0
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/* I2S_LRCK_CTRL1 */
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#define LRCK_POLARITY 4
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#define LRCK_PERIODH 0
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/* I2S_LRCK_CTRL2 */
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#define LRCK_PERIODL 0
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/* I2S_FMT_CTRL1 */
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#define ENCD_FMT 7
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#define ENCD_SEL 6
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#define MODE_SEL 4
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#define TX_OFFSET 2
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#define TX_SLOT_HIZ 1
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#define TX_STATE 0
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/* I2S_FMT_CTRL2 */
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#define SLOT_WIDTH_SEL 4
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#define SAMPLE_RESOLUTION 0
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/* I2S_FMT_CTRL3 */
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#define TX_MLS 7
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#define SEXT 5
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#define SDOUT_MUTE 3
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#define LRCK_WIDTH 2
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#define TX_PDM 0
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/* I2S_TX_CTRL1 */
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#define TX_CHSEL 0
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/* I2S_TX_CTRL2 */
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#define TX_CH8_EN 7
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#define TX_CH7_EN 6
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#define TX_CH6_EN 5
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#define TX_CH5_EN 4
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#define TX_CH4_EN 3
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#define TX_CH3_EN 2
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#define TX_CH2_EN 1
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#define TX_CH1_EN 0
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/* I2S_TX_CTRL3 */
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#define TX_CH16_EN 7
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#define TX_CH15_EN 6
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#define TX_CH14_EN 5
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#define TX_CH13_EN 4
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#define TX_CH12_EN 3
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#define TX_CH11_EN 2
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#define TX_CH10_EN 1
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#define TX_CH9_EN 0
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/* I2S_TX_CHMP_CTRL1 */
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#define TX_CH8_MAP 7
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#define TX_CH7_MAP 6
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#define TX_CH6_MAP 5
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#define TX_CH5_MAP 4
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#define TX_CH4_MAP 3
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#define TX_CH3_MAP 2
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#define TX_CH2_MAP 1
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#define TX_CH1_MAP 0
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/* I2S_TX_CHMP_CTRL2 */
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#define TX_CH16_MAP 7
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#define TX_CH15_MAP 6
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#define TX_CH14_MAP 5
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#define TX_CH13_MAP 4
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#define TX_CH12_MAP 3
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#define TX_CH11_MAP 2
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#define TX_CH10_MAP 1
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#define TX_CH9_MAP 0
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/* I2S_RX_CTRL1 */
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#define RX_CHSEL 0
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/* I2S_RX_CTRL2 */
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#define RX_CH8_EN 7
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#define RX_CH7_EN 6
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#define RX_CH6_EN 5
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#define RX_CH5_EN 4
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#define RX_CH4_EN 3
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#define RX_CH3_EN 2
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#define RX_CH2_EN 1
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#define RX_CH1_EN 0
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/* I2S_RX_CTRL3 */
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#define RX_CH16_EN 7
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#define RX_CH15_EN 6
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#define RX_CH14_EN 5
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#define RX_CH13_EN 4
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#define RX_CH12_EN 3
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#define RX_CH11_EN 2
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#define RX_CH10_EN 1
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#define RX_CH9_EN 0
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/* I2S_RX_CHMP_CTRL1 */
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#define RX_CH8_MAP 7
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#define RX_CH7_MAP 6
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#define RX_CH6_MAP 5
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#define RX_CH5_MAP 4
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#define RX_CH4_MAP 3
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#define RX_CH3_MAP 2
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#define RX_CH2_MAP 1
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#define RX_CH1_MAP 0
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/* I2S_RX_CHMP_CTRL2 */
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#define RX_CH16_MAP 7
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#define RX_CH15_MAP 6
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#define RX_CH14_MAP 5
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#define RX_CH13_MAP 4
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#define RX_CH12_MAP 3
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#define RX_CH11_MAP 2
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#define RX_CH10_MAP 1
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#define RX_CH9_MAP 0
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/* PDM_CTRL */
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#define PDM_TIMING 1
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#define PDM_EN 0
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/*ADC_SPRC*/
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#define ADC_FS_I2S 0
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/* ADC_DIG_EN */
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#define REQ_WIDTH 4
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#define REQ_EN 3
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#define DG_EN 2
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#define ENAD2 1
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#define ENAD1 0
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/* DMIC_EN */
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#define DIG_MIC_EN 0
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/* HPF_EN */
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#define DIG_ADC2_HPF_EN 1
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#define DIG_ADC1_HPF_EN 0
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/* ADC1_DMIX_SRC */
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#define ADC1_ADC2_DMXL_GC 3
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#define ADC1_ADC1_DMXL_GC 2
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#define ADC1_ADC2_DMXL_SRC 1
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#define ADC1_ADC1_DMXL_SRC 0
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/* ADC2_DMIX_SRC */
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#define ADC2_ADC2_DMXL_GC 3
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#define ADC2_ADC1_DMXL_GC 2
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#define ADC2_ADC2_DMXL_SRC 1
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#define ADC2_ADC1_DMXL_SRC 0
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/* ADC_DIG_DEBUG */
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#define I2S_LPB_DEBUG 3
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#define ADC_PTN_SEL 0
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/* ADC_ANA_DEBUG1 */
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#define DMIC_CLK_PAD_SEL 4
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#define DMIC_DAT_PAD_SEL 0
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/* ADC_ANA_DEBUG2 */
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#define DEV_ID1_PAD_SEL 4
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#define DEV_ID0_PAD_SEL 0
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/* I2S_PADDRV_CTRL */
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#define MCLK_DRV 6
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#define BCLK_DRV 4
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#define LRCK_DRV 2
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#define SDOUT_DRV 0
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/* ANA_ADC1_CTRL1 */
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#define RX1_PGA_OI_CTRL 5
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#define RX1_PGA_AMP_IB_SEL 2
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#define RX1_PGA_IN_VCM_CTRL 0
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/* ANA_ADC1_CTRL2 */
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#define RX1_PGA_OI_NM_CTRL 3
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#define RX1_PGA_NMAMP_IB_SEL 0
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/* ANA_ADC1_CTRL3 */
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#define RX1_PGA_CTRL_RCM 5
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#define RX1_PGA_GAIN_CTRL 0
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/* ANA_ADC1_CTRL4 */
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#define RX1_DSM_OTA_IB_SEL 5
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#define RX1_DSM_COMP_IB_SEL 2
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#define RX1_DSM_OTA_CTRL 0
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/* ANA_ADC1_CTRL5 */
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#define RX1_GLOBAL_EN 6
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#define RX1_DSM_DISABLE 5
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#define RX1_DSM_DEMOFF 4
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#define RX1_SEL_OUT_EDGE 3
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#define RX1_DSM_VRP_LPMODE 2
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#define RX1_DSM_VRP_OUTCTRL 0
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/* ANA_ADC2_CTRL1 */
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#define RX2_PGA_OI_CTRL 5
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#define RX2_PGA_AMP_IB_SEL 2
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#define RX2_PGA_IN_VCM_CTRL 0
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/* ANA_ADC2_CTRL2 */
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#define RX2_PGA_OI_NM_CTRL 3
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#define RX2_PGA_NMAMP_IB_SEL 0
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/* ANA_ADC2_CTRL3 */
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#define RX2_PGA_CTRL_RCM 5
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#define RX2_PGA_GAIN_CTRL 0
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/* ANA_ADC2_CTRL4 */
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#define RX2_DSM_OTA_IB_SEL 5
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#define RX2_DSM_COMP_IB_SEL 2
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#define RX2_DSM_OTA_CTRL 0
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/* ANA_ADC2_CTRL5 */
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#define RX2_GLOBAL_EN 6
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#define RX2_DSM_DISABLE 5
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#define RX2_DSM_DEMOFF 4
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#define RX2_SEL_OUT_EDGE 3
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#define RX2_DSM_VRP_LPMODE 2
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#define RX2_DSM_VRP_OUTCTRL 0
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/* ADC_DITHER_CTRL */
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#define DSM_DITHER_CTRL 4
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#define DSM_DITHER_EN 3
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#define DSM_DITHER_LVL 0
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/*** Some Config Value ***/
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//PLLCLK_SRC
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#define PLLCLK_SRC_MCLK 0
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#define PLLCLK_SRC_BCLK 1
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#define PLLCLK_SRC_PDMCLK 2
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//SYSCLK_SRC
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#define SYSCLK_SRC_MCLK 0
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#define SYSCLK_SRC_BCLK 1
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#define SYSCLK_SRC_PLL 2
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//I2S BCLK POLARITY Control
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#define BCLK_NORMAL_DRIVE_N_SAMPLE_P 0
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#define BCLK_INVERT_DRIVE_P_SAMPLE_N 1
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//I2S LRCK POLARITY Control
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#define LRCK_LEFT_LOW_RIGHT_HIGH 0
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#define LRCK_LEFT_HIGH_RIGHT_LOW 1
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//I2S Format Selection
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#define PCM_FORMAT 0
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#define LEFT_JUSTIFIED_FORMAT 1
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#define RIGHT_JUSTIFIED_FORMAT 2
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//I2S Sign Extend in slot
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#define ZERO_OR_AUDIIO_GAIN_PADDING_LSB 0
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#define SIGN_EXTENSION_MSB 1
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#define TRANSFER_ZERO_AFTER 3
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//ADC Digital Debug Control
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#define ADC_PTN_NORMAL 0
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#define ADC_PTN_0x5A5A5A 1
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#define ADC_PTN_0x123456 2
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#define ADC_PTN_ZERO 3
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#define ADC_PTN_I2S_RX_DATA 4
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//ADC PGA GAIN Control
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#define ADC_PGA_GAIN_MINUS_6dB 0
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#define ADC_PGA_GAIN_0dB 1
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#define ADC_PGA_GAIN_3dB 4
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#define ADC_PGA_GAIN_4dB 5
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#define ADC_PGA_GAIN_5dB 6
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#define ADC_PGA_GAIN_6dB 7
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#define ADC_PGA_GAIN_7dB 8
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#define ADC_PGA_GAIN_8dB 9
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#define ADC_PGA_GAIN_9dB 10
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#define ADC_PGA_GAIN_10dB 11
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#define ADC_PGA_GAIN_11dB 12
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#define ADC_PGA_GAIN_12dB 13
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#define ADC_PGA_GAIN_13dB 14
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#define ADC_PGA_GAIN_14dB 15
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#define ADC_PGA_GAIN_15dB 16
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#define ADC_PGA_GAIN_16dB 17
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#define ADC_PGA_GAIN_17dB 18
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#define ADC_PGA_GAIN_18dB 19
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#define ADC_PGA_GAIN_19dB 20
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#define ADC_PGA_GAIN_20dB 21
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#define ADC_PGA_GAIN_21dB 22
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#define ADC_PGA_GAIN_22dB 23
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#define ADC_PGA_GAIN_23dB 24
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#define ADC_PGA_GAIN_24dB 25
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#define ADC_PGA_GAIN_25dB 26
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#define ADC_PGA_GAIN_26dB 27
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#define ADC_PGA_GAIN_27dB 28
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#define ADC_PGA_GAIN_28dB 29
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#define ADC_PGA_GAIN_29dB 30
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#define ADC_PGA_GAIN_30dB 31
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#endif
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