153 lines
4.3 KiB
C
153 lines
4.3 KiB
C
/*
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* Copyright (c) 2019-2025 Allwinner Technology Co., Ltd. ALL rights reserved.
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*
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* Allwinner is a trademark of Allwinner Technology Co.,Ltd., registered in
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* the the People's Republic of China and other countries.
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* All Allwinner Technology Co.,Ltd. trademarks are used with permission.
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*
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* DISCLAIMER
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* THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT.
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* IF YOU NEED TO INTEGRATE THIRD PARTY’S TECHNOLOGY (SONY, DTS, DOLBY, AVS OR MPEGLA, ETC.)
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* IN ALLWINNERS’SDK OR PRODUCTS, YOU SHALL BE SOLELY RESPONSIBLE TO OBTAIN
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* ALL APPROPRIATELY REQUIRED THIRD PARTY LICENCES.
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* ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS
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* COVERED UNDER ANY REQUIRED THIRD PARTY LICENSE.
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* YOU ARE SOLELY RESPONSIBLE FOR YOUR USAGE OF THIRD PARTY’S TECHNOLOGY.
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*
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*
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* THIS SOFTWARE IS PROVIDED BY ALLWINNER"AS IS" AND TO THE MAXIMUM EXTENT
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* PERMITTED BY LAW, ALLWINNER EXPRESSLY DISCLAIMS ALL WARRANTIES OF ANY KIND,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION REGARDING
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* THE TITLE, NON-INFRINGEMENT, ACCURACY, CONDITION, COMPLETENESS, PERFORMANCE
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* OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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* IN NO EVENT SHALL ALLWINNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS, OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "soc.h"
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#include <core_rv32.h>
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#include <hal_interrupt.h>
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#define CONFIG_CPU_E907FD 1
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static int g_system_clock = IHS_VALUE;
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extern void irq_vectors_init(void);
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extern int __Vectors;
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extern void dcache_enable(void);
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int32_t drv_get_sys_freq(void)
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{
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return g_system_clock;
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}
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static void _system_init_for_kernel(void)
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{
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irq_vectors_init();
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csi_coret_config(drv_get_sys_freq() / CONFIG_HZ, CORET_IRQn); //10ms
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hal_enable_irq(CORET_IRQn);
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}
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void SystemInit(void)
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{
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int i;
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uint32_t mstatus = 0;
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/* enable mstatus FS */
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#ifdef CONFIG_ARCH_RISCV_FPU
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mstatus = __get_MSTATUS();
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mstatus |= (1 << 13);
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__set_MSTATUS(mstatus);
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#endif
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/* enable mxstatus THEADISAEE */
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uint32_t mxstatus = __get_MXSTATUS();
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mxstatus |= (1 << 22);
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/* enable mxstatus MM */
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#ifdef CONFIG_ARCH_RISCV_FPU
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mxstatus |= (1 << 15);
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#endif
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__set_MXSTATUS(mxstatus);
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/* get interrupt level from info */
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CLIC->CLICCFG = (((CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos) << CLIC_CLICCFG_NLBIT_Pos);
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for (i = 0; i < sizeof(CLIC->CLICINT)/sizeof(CLIC->CLICINT[0]); i++)
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{
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CLIC->CLICINT[i].IP = 0;
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CLIC->CLICINT[i].ATTR = 1; /* use vector interrupt */
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}
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/* tspend use positive interrupt */
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CLIC->CLICINT[Machine_Software_IRQn].ATTR = 0x3;
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hal_enable_irq(Machine_Software_IRQn);
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_system_init_for_kernel();
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}
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/* enable mexstatus SPUSHEN and SPSWAPEN */
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#ifdef CONFIG_ARCH_RISCV_FPU
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void context_mexstatus(void)
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{
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unsigned int mexstatus;
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mexstatus = __get_MEXSTATUS();
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mexstatus |= (0x2 << 16);
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__set_MEXSTATUS(mexstatus);
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}
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#endif
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#ifdef CONFIG_STANDBY
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void clic_suspend(void)
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{
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return;
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}
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void clic_resume(void)
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{
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int i;
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uint32_t mstatus = 0;
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/* enable mstatus FS */
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#ifdef CONFIG_ARCH_RISCV_FPU
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mstatus = __get_MSTATUS();
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mstatus |= (1 << 13);
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__set_MSTATUS(mstatus);
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#endif
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/* enable mxstatus THEADISAEE */
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uint32_t mxstatus = __get_MXSTATUS();
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mxstatus |= (1 << 22);
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/* enable mxstatus MM */
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#ifdef CONFIG_ARCH_RISCV_FPU
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mxstatus |= (1 << 15);
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#endif
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__set_MXSTATUS(mxstatus);
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/* get interrupt level from info */
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CLIC->CLICCFG = (((CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos) << CLIC_CLICCFG_NLBIT_Pos);
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for (i = 0; i < sizeof(CLIC->CLICINT)/sizeof(CLIC->CLICINT[0]); i++)
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{
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CLIC->CLICINT[i].IP = 0;
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CLIC->CLICINT[i].ATTR = 1; /* use vector interrupt */
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}
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/* tspend use positive interrupt */
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CLIC->CLICINT[Machine_Software_IRQn].ATTR = 0x3;
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csi_coret_config(drv_get_sys_freq() / CONFIG_HZ, CORET_IRQn);
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hal_enable_irq(CORET_IRQn);
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dcache_enable();
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}
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#endif
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