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sdk-hwV1.3/lichee/linux-4.9/arch/arm/boot/dts/sun8iw18p1.dtsi

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/*
* Allwinner Technology CO., Ltd. sun8iw18p1 platform
*
* modify base on juno.dts
*/
/* optee used 4M: SHM 1M, OS 1M, TA 6M*/
/memreserve/ 0x41800000 0x00800000;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
#include "sun8iw18p1-clk.dtsi"
#include "sun8iw18p1-pinctrl.dtsi"
/ {
model = "sun8iw18";
compatible = "allwinner,sun8iw18p1";
interrupt-parent = <&wakeupgen>;
#address-cells = <2>;
#size-cells = <2>;
aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
twi0 = &twi0;
twi1 = &twi1;
spi0 = &spi0;
spinand = &spinand;
spi1 = &spi1;
global_timer0 = &soc_timer0;
ledc = &ledc;
nand0 =&nand0;
pwm = &pwm;
pwm0 = &pwm0;
pwm1 = &pwm1;
pwm2 = &pwm2;
pwm3 = &pwm3;
pwm4 = &pwm4;
pwm5 = &pwm5;
pwm6 = &pwm6;
pwm7 = &pwm7;
boot_disp = &boot_disp;
lcd_fb0 = &lcd_fb0;
lcdfb = &lcdfb;
};
chosen {
bootargs = "earlyprintk=sunxi-uart,0x05000000 loglevel=8 initcall_debug=0 console=ttyS0,115200 init=/init";
linux,initrd-start = <0x0 0x0>;
linux,initrd-end = <0x0 0x0>;
};
firmware {
android {
compatible = "android,firmware";
name = "android";
fstab {
compatible = "android,fstab";
name = "fstab";
vendor {
compatible = "android,vendor";
dev = "/dev/block/by-name/vendor";
fsmgr_flags = "wait";
mnt_flags = "ro,barrier=1";
name = "vendor";
status = "ok";
type = "ext4";
};
system {
compatible = "android,system";
dev = "/dev/block/by-name/system";
fsmgr_flags = "wait";
mnt_flags = "ro,barrier=1";
name = "system";
status = "ok";
type = "ext4";
};
};
};
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};
cpus {
enable-method = "allwinner,sun8iw18p1";
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7","arm,armv7";
reg = <0x0>;
enable-method = "psci";
clocks = <&clk_pll_cpu>,<&clk_cpu>,<&clk_pll_periph0>;
clock-names = "pll","cpu","periph0";
operating-points-v2 = <&cpu_opp_l_table0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0 &SYS_SLEEP_0>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a7","arm,armv7";
reg = <0x1>;
enable-method = "psci";
clocks = <&clk_pll_cpu>,<&clk_cpu>,<&clk_pll_periph0>;
clock-names = "pll","cpu","periph0";
operating-points-v2 = <&cpu_opp_l_table0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0 &SYS_SLEEP_0>;
};
idle-states {
entry-method = "arm,psci";
CPU_SLEEP_0: cpu-sleep-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0010000>;
entry-latency-us = <140>;
exit-latency-us = <540>;
min-residency-us = <4800>;
};
CLUSTER_SLEEP_0: cluster-sleep-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x1010000>;
entry-latency-us = <500>;
exit-latency-us = <1000>;
min-residency-us = <10000>;
};
SYS_SLEEP_0: sys-sleep-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x2010000>;
entry-latency-us = <2000000>;
exit-latency-us = <2000000>;
min-residency-us = <2000000>;
};
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
dvfs_table: dvfs_table {
compatible = "allwinner,dvfs_table";
};
n_brom {
compatible = "allwinner,n-brom";
reg = <0x0 0x0 0x0 0xc000>;
};
s_brom {
compatible = "allwinner,s-brom";
reg = <0x0 0x0 0x0 0x10000>;
};
sram_ctrl {
device_type = "sram_ctrl";
compatible = "allwinner,sram_ctrl";
reg = <0x0 0x03000000 0x0 0x100>;
};
sram_a1 {
compatible = "allwinner,sram_a1";
reg = <0x0 0x00010000 0x0 0x10000>;
};
sram_a2 {
compatible = "allwinner,sram_a2";
reg = <0x0 0x00040000 0x0 0x14000>;
};
prcm {
compatible = "allwinner,prcm";
reg = <0x0 0x01f01400 0x0 0x400>;
};
cpuscfg {
compatible = "allwinner,cpuscfg";
reg = <0x0 0x01f01c00 0x0 0x400>;
};
ion {
compatible = "allwinner,sunxi-ion";
/*
*types list here:
ION_HEAP_TYPE_SYSTEM = 0,
ION_HEAP_TYPE_SYSTEM_CONTIG = 1,
ION_HEAP_TYPE_CARVEOUT = 2,
ION_HEAP_TYPE_CHUNK = 3,
ION_HEAP_TYPE_DMA = 4,
ION_HEAP_TYPE_SECURE = 6,
**/
heap_sys_user@0{
compatible = "allwinner,sys_user";
heap-name = "sys_user";
heap-id = <0x0>;
heap-base = <0x0>;
heap-size = <0x0>;
heap-type = "ion_system";
};
heap_sys_contig@0{
compatible = "allwinner,sys_contig";
heap-name = "sys_contig";
heap-id = <0x1>;
heap-base = <0x0>;
heap-size = <0x0>;
heap-type = "ion_contig";
};
heap_cma@0{
compatible = "allwinner,cma";
heap-name = "cma";
heap-id = <0x4>;
heap-base = <0x0>;
heap-size = <0x0>;
heap-type = "ion_cma";
};
heap_secure@0{
compatible = "allwinner,secure";
heap-name = "secure";
heap-id = <0x6>;
heap-base = <0x0>;
heap-size = <0x0>;
heap-type = "ion_secure";
};
};
dram: dram {
compatible = "allwinner,dram";
/* clocks = <&clk_pll_ddr>; */
clock-names = "pll_ddr";
dram_clk = <672>;
dram_type = <3>;
dram_zq = <0x003F3FDD>;
dram_odt_en = <1>;
dram_para1 = <0x10f41000>;
dram_para2 = <0x00001200>;
dram_mr0 = <0x1A50>;
dram_mr1 = <0x40>;
dram_mr2 = <0x10>;
dram_mr3 = <0>;
dram_tpr0 = <0x04E214EA>;
dram_tpr1 = <0x004214AD>;
dram_tpr2 = <0x10A75030>;
dram_tpr3 = <0>;
dram_tpr4 = <0>;
dram_tpr5 = <0>;
dram_tpr6 = <0>;
dram_tpr7 = <0>;
dram_tpr8 = <0>;
dram_tpr9 = <0>;
dram_tpr10 = <0>;
dram_tpr11 = <0>;
dram_tpr12 = <168>;
dram_tpr13 = <0x823>;
};
memory@40000000 {
device_type = "memory";
reg = <0x00000000 0x40000000 0x00000000 0x4000000>;
};
gic: interrupt-controller@03020000 {
compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
device_type = "gic";
interrupt-controller;
reg = <0x0 0x03021000 0 0x1000>, /* GIC Dist */
<0x0 0x03022000 0 0x2000>, /* GIC CPU */
<0x0 0x03024000 0 0x2000>, /* GIC VCPU Control */
<0x0 0x03026000 0 0x2000>; /* GIC VCPU */
interrupts = <GIC_PPI 9 0xf04>; /* GIC Maintenence IRQ */
interrupt-parent = <&gic>;
};
wakeupgen: interrupt-controller@0 {
compatible = "allwinner,sunxi-wakeupgen";
interrupt-controller;
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
};
sid: sunxi-sid@03006000 {
compatible = "allwinner,sunxi-sid";
device_type = "sid";
reg = <0x0 0x03006000 0 0x200>;
};
chipid: sunxi-chipid@03006200 {
compatible = "allwinner,sunxi-chipid";
device_type = "chipid";
reg = <0x0 0x03006200 0 0x80>;
};
timer_arch {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <24000000>;
arm,cpu-registers-not-fw-configured;
interrupt-parent = <&gic>;
};
pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
};
dvfs_table: dvfs_table {
compatible = "allwinner,dvfs_table";
max_freq = <1200000000>;
min_freq = <480000000>;
lv_count = <8>;
lv1_freq = <1200000000>;
lv1_volt = <1300>;
lv2_freq = <1008000000>;
lv2_volt = <1200>;
lv3_freq = <816000000>;
lv3_volt = <1100>;
lv4_freq = <648000000>;
lv4_volt = <1040>;
lv5_freq = <0>;
lv5_volt = <1040>;
lv6_freq = <0>;
lv6_volt = <1040>;
lv7_freq = <0>;
lv7_volt = <1040>;
lv8_freq = <0>;
lv8_volt = <1040>;
};
dram_opp_table: dram_opp_table {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <264000000>;
opp-microvolt = <900000>;
};
opp01 {
opp-hz = /bits/ 64 <528000000>;
opp-microvolt = <900000>;
};
};
dramfreq {
compatible = "dramfreq-sun8iw18p1";
reg = <0x0 0x04002000 0x0 0x400>,
<0x0 0x04003000 0x0 0x800>,
<0x0 0x03001000 0x0 0x800>;
clocks = <&clk_sdram>;
operating-points-v2 = <&dram_opp_table>;
};
uboot: uboot {
};
soc: soc@03000000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
device_type = "soc";
dma0:dma-controller@03002000 {
compatible = "allwinner,sun8i-dma";
reg = <0x0 0x03002000 0x0 0x1000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_dma>;
#dma-cells = <1>;
};
mbus0:mbus-controller@04002000 {
compatible = "allwinner,sun8i-mbus";
reg = <0x0 0x04002000 0x0 0x1000>;
#mbus-cells = <1>;
};
standby_space {
compatible = "allwinner,sun8iw18-superstandby";
/* num dst offset size */
space1 = <0x40020000 0x00000000 0x00000800>; /* super standby para space */
};
soc_timer0: timer@03009000 {
compatible = "allwinner,sun4i-a10-timer";
device_type = "soc_timer";
reg = <0x0 0x03009000 0x0 0x90>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_hosc>, <&clk_losc>;
};
soc_timer1@03009000{
compatible = "allwinner,timer_alarm";
reg = <0x0 0x03009000 0x0 0x90>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
wakeup-source;
};
rtc: rtc@07000000 {
compatible = "allwinner,sunxi-rtc";
device_type = "rtc";
clocks = <&clk_losc_ext>;
reg = <0x0 0x07000000 0x0 0x400>;
clk32k_out = <0>; /* 0:disable out, 1:enable output */
gpr_offset = <0x100>;
gpr_len = <8>;
gpr_cur_pos = <6>;
gpr_bootcount_pos = <7>;
};
wdt: watchdog@030090a0 {
compatible = "allwinner,sun50i-wdt";
reg = <0x0 0x030090a0 0x0 0x20>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
};
uart0: uart@05000000 {
compatible = "allwinner,sun8i-uart";
device_type = "uart0";
reg = <0x0 0x05000000 0x0 0x400>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_uart0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&uart0_pins_a>;
pinctrl-1 = <&uart0_pins_b>;
uart0_port = <0>;
uart0_type = <2>;
status = "okay";
};
uart1: uart@05000400 {
compatible = "allwinner,sun8i-uart";
device_type = "uart1";
reg = <0x0 0x05000400 0x0 0x400>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_uart1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&uart1_pins_a>;
pinctrl-1 = <&uart1_pins_b>;
uart1_port = <1>;
uart1_type = <4>;
status = "disabled";
};
uart2: uart@05000800 {
compatible = "allwinner,sun8i-uart";
device_type = "uart2";
reg = <0x0 0x05000800 0x0 0x400>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_uart2>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&uart2_pins_a>;
pinctrl-1 = <&uart2_pins_b>;
uart2_port = <2>;
uart2_type = <4>;
status = "disabled";
};
uart3: uart@05000c00 {
compatible = "allwinner,sun8i-uart";
device_type = "uart3";
reg = <0x0 0x05000c00 0x0 0x400>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_uart3>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&uart3_pins_a>;
pinctrl-1 = <&uart3_pins_b>;
uart3_port = <3>;
uart3_type = <4>;
status = "disabled";
};
twi0: twi@0x05002000{
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sun8i-twi";
device_type = "twi0";
reg = <0x0 0x05002000 0x0 0x400>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_twi0>;
clock-frequency = <400000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&twi0_pins_a>;
pinctrl-1 = <&twi0_pins_b>;
status = "disabled";
};
twi1: twi@0x05002400{
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sun8i-twi";
device_type = "twi1";
reg = <0x0 0x05002400 0x0 0x400>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_twi1>;
clock-frequency = <100000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&twi1_pins_a>;
pinctrl-1 = <&twi1_pins_b>;
status = "disabled";
};
usbc0:usbc0@0 {
device_type = "usbc0";
compatible = "allwinner,sunxi-otg-manager";
usb_port_type = <2>;
usb_detect_type = <1>;
usb_id_gpio;
usb_det_vbus_gpio;
usb_drv_vbus_gpio;
usb_host_init_state = <0>;
usb_regulator_io = "nocare";
usb_wakeup_suspend = <0>;
usb_luns = <3>;
usb_serial_unique = <0>;
usb_serial_number = "20080411";
rndis_wceis = <1>;
status = "okay";
};
udc:udc-controller@0x05100000 {
compatible = "allwinner,sunxi-udc";
reg = <0x0 0x05100000 0x0 0x1000>, /*udc base*/
<0x0 0x00000000 0x0 0x100>; /*sram base*/
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_usbphy0>, <&clk_usbotg>;
status = "okay";
};
ehci0:ehci0-controller@0x05101000 {
compatible = "allwinner,sunxi-ehci0";
reg = <0x0 0x05101000 0x0 0xFFF>, /*hci0 base*/
<0x0 0x00000000 0x0 0x100>, /*sram base*/
<0x0 0x05100000 0x0 0x1000>; /*otg base*/
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_usbphy0>, <&clk_usbehci0>;
hci_ctrl_no = <0>;
status = "okay";
};
ohci0:ohci0-controller@0x05101400 {
compatible = "allwinner,sunxi-ohci0";
reg = <0x0 0x05101000 0x0 0xFFF>, /*hci0 base*/
<0x0 0x00000000 0x0 0x100>, /*sram base*/
<0x0 0x05100000 0x0 0x1000>; /*otg base*/
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_usbphy0>, <&clk_usbohci0>, <&clk_usbohci0_12m>, <&clk_osc48md4>, <&clk_hosc>, <&clk_losc>;
hci_ctrl_no = <0>;
status = "okay";
};
daudio0:daudio@0x05090000 {
compatible = "allwinner,sunxi-daudio";
reg = <0x0 0x05090000 0x0 0x7c>;
clocks = <&clk_pll_audio>,<&clk_pll_audiox4>,<&clk_i2s0>;
pinctrl-names = "default", "default", "sleep";
pinctrl-0 = <&daudio0_pins_a>;
pinctrl-1 = <&daudio0_pins_b>;
pinctrl-2 = <&daudio0_pins_c>;
pcm_lrck_period = <0x80>;
slot_width_select = <0x20>;
frametype = <0x00>;
tdm_config = <0x01>;
tdm_num = <0x0>;
mclk_div = <0x0>;
status = "disabled";
};
daudio1:daudio@0x05091000 {
compatible = "allwinner,sunxi-daudio";
reg = <0x0 0x05091000 0x0 0x7c>;
clocks = <&clk_pll_audio>,<&clk_pll_audiox4>,<&clk_i2s1>;
pinctrl-names = "default", "default", "sleep";
pinctrl-0 = <&daudio1_pins_a>;
pinctrl-1 = <&daudio1_pins_b>;
pinctrl-2 = <&daudio1_pins_c>;
pcm_lrck_period = <0x40>;
slot_width_select = <0x10>;
frametype = <0x00>;
tdm_config = <0x01>;
tdm_num = <0x1>;
mclk_div = <0x1>;
status = "disabled";
};
daudio2:daudio@0x05092000 {
compatible = "allwinner,sunxi-daudio";
reg = <0x0 0x05092000 0x0 0x7c>;
clocks = <&clk_pll_audio>,<&clk_pll_audiox4>,<&clk_i2s2>;
pinctrl-names = "default", "default", "sleep";
pinctrl-0 = <&daudio2_pins_a>;
pinctrl-1 = <&daudio2_pins_b>;
pinctrl-2 = <&daudio2_pins_c>;
pcm_lrck_period = <0x20>;
slot_width_select = <0x20>;
frametype = <0x00>;
tdm_config = <0x01>;
tdm_num = <0x2>;
mclk_div = <0x0>;
status = "disabled";
};
spdif:spdif-controller@0x05093000 {
compatible = "allwinner,sunxi-spdif";
reg = <0x0 0x05093000 0x0 0x40>;
clocks = <&clk_pll_audio>,<&clk_pll_audiox4>,<&clk_spdif>;
pinctrl-names = "default", "default", "sleep";
pinctrl-0 = <&spdif_pins_a>;
pinctrl-1 = <&spdif_pins_b>;
pinctrl-2 = <&spdif_pins_c>;
status = "disabled";
};
dmic:dmic-controller@0x05095000 {
compatible = "allwinner,sunxi-dmic";
reg = <0x0 0x05095000 0x0 0x50>;
clocks = <&clk_pll_audio>,<&clk_pll_audiox4>,<&clk_dmic>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&dmic_pins_a>;
pinctrl-1 = <&dmic_pins_b>;
status = "disabled";
};
codec:codec@0x05096000 {
compatible = "allwinner,sunxi-internal-codec";
reg = <0x0 0x05096000 0x0 0x2c0>,/*digital baseadress*/
<0x0 0x05096300 0x0 0x4>,/*analog baseadress*/
<0x0 0x05090000 0x0 0x7c>,/* i2s0 */
<0x0 0x05091000 0x0 0x7c>,/* i2s1 */
<0x0 0x05092000 0x0 0x7c>;/* i2s2 */
clocks = <&clk_pll_audio>,<&clk_pll_audiox4>,<&clk_codec_1x>,
<&clk_i2s0>,<&clk_i2s1>,<&clk_i2s2>;
gpio-spk = <&pio PH 9 1 1 1 1>;
pa_ctl_level = <0x1>;
digital_vol = <0x0>;
lineout_vol = <0x1f>;
mic1gain = <0x4>;
mic2gain = <0x4>;
mic3gain = <0x4>;
adcgain = <0x3>;
adcdrc_cfg = <0x0>;
adchpf_cfg = <0x0>;
dacdrc_cfg = <0x0>;
dachpf_cfg = <0x0>;
pa_msleep_time = <0xa0>;
status = "disabled";
};
cpudai:cpudai-controller@0x05096000 {
compatible = "allwinner,sunxi-internal-cpudai";
reg = <0x0 0x05096000 0x0 0x2c0>;/*digital baseadress*/
status = "disabled";
};
mad:mad@0x05400000{
compatible = "allwinner,sunxi-mad";
reg = <0x0 0x05400000 0x0 0x3ff>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "lpsd-irq", "mad-irq";
wakeup-source;
clocks = <&clk_pll_audio>,<&clk_hosc>,<&clk_lpsd>,
<&clk_mad>,<&clk_mad_ad>,<&clk_mad_cfg>;
lpsd_clk_src_cfg = <0x0>;
/* IO:0x1, MEMORY:0x0 */
standby_sram_io_type = <0x0>;
status = "disabled";
};
sndcodec:sound@0 {
compatible = "allwinner,sunxi-codec-machine";
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
sunxi,cpudai-controller = <&cpudai>;
sunxi,audio-codec = <&codec>;
status = "disabled";
};
snddaudio0:sound@1{
compatible = "allwinner,sunxi-daudio0-machine";
sunxi,daudio-controller = <&daudio0>;
sunxi,snddaudio-codec = "snd-soc-dummy";
sunxi,snddaudio-codec-dai = "snd-soc-dummy-dai";
daudio_master = <0x04>;
audio_format = <0x01>;
signal_inversion = <0x01>;
status = "disabled";
};
snddaudio1:sound@2{
compatible = "allwinner,sunxi-daudio1-machine";
sunxi,daudio-controller = <&daudio1>;
daudio_master = <0x04>;
audio_format = <0x01>;
signal_inversion = <0x01>;
status = "disabled";
};
snddaudio2:sound@3{
compatible = "allwinner,sunxi-daudio2-machine";
sunxi,daudio-controller = <&daudio2>;
daudio_master = <0x04>;
audio_format = <0x01>;
signal_inversion = <0x01>;
status = "disabled";
};
sndspdif:sound@4{
compatible = "allwinner,sunxi-spdif-machine";
sunxi,spdif-controller = <&spdif>;
status = "disabled";
};
snddmic:sound@5{
compatible = "allwinner,sunxi-dmic-machine";
sunxi,dmic-controller = <&dmic>;
status = "disabled";
};
spi0: spi@05010000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sun8i-spi";
device_type = "spi0";
reg = <0x0 0x05010000 0x0 0x1000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_pll_periph0>, <&clk_spi0>;
clock-frequency = <100000000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&spi0_pins_a &spi0_pins_b>;
pinctrl-1 = <&spi0_pins_c>;
spi0_cs_number = <2>;
spi0_cs_bitmap = <3>;
status = "disabled";
};
spinand: spinand@05010000 {
compatible = "allwinner,sunxi-spinand", "allwinner,sunxi-mtd-spinand";
device_type = "spinand";
reg = <0x0 0x05010000 0x0 0x1000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_pll_periph0>, <&clk_spi0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&spi0_pins_a &spi0_pins_b>;
pinctrl-1 = <&spi0_pins_c>;
nand0_regulator1 = "vcc-nand";
nand0_regulator2 = "none";
nand0_cache_level = <0x55aaaa55>;
nand0_flush_cache_num = <0x55aaaa55>;
nand0_capacity_level = <0x55aaaa55>;
nand0_id_number_ctl = <0x55aaaa55>;
nand0_print_level = <0x55aaaa55>;
nand0_p0 = <0x55aaaa55>;
nand0_p1 = <0x55aaaa55>;
nand0_p2 = <0x55aaaa55>;
nand0_p3 = <0x55aaaa55>;
status = "disabled";
};
spi1: spi@05011000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sun8i-spi";
device_type = "spi1";
reg = <0x0 0x05011000 0x0 0x1000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_pll_periph0>, <&clk_spi1>;
clock-frequency = <100000000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&spi1_pins_a &spi1_pins_b>;
pinctrl-1 = <&spi1_pins_c>;
spi1_cs_number = <1>;
spi1_cs_bitmap = <1>;
status = "okay";
};
sdc1: sdmmc@04021000 {
compatible = "allwinner,sunxi-mmc-v4p1x";
device_type = "sdc1";
reg = <0x0 0x04021000 0x0 0x1000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_hosc>,
<&clk_pll_periph1x2>,
<&clk_sdmmc1_mod>,
<&clk_sdmmc1_bus>,
<&clk_sdmmc1_rst>;
clock-names = "osc24m","pll_periph","mmc","ahb","rst";
pinctrl-names = "default","sleep";
pinctrl-0 = <&sdc1_pins_a>;
pinctrl-1 = <&sdc1_pins_b>;
max-frequency = <50000000>;
bus-width = <4>;
/*broken-cd;*/
/*cd-inverted*/
/*cd-gpios = <&pio PG 6 6 1 2 0>;*/
/* vmmc-supply = <&reg_3p3v>;*/
/* vqmc-supply = <&reg_3p3v>;*/
/* vdmc-supply = <&reg_3p3v>;*/
/*vmmc = "vcc-card";*/
/*vqmc = "";*/
/*vdmc = "";*/
cap-sd-highspeed;
no-mmc;
/*sd-uhs-sdr50;*/
/*sd-uhs-ddr50;*/
/*sd-uhs-sdr104;*/
/*cap-sdio-irq;*/
keep-power-in-suspend;
/*ignore-pm-notify;*/
/*sunxi-power-save-mode;*/
/*sunxi-dly-400k = <1 0 0 0 0>; */
/*sunxi-dly-26M = <1 0 0 0 0>;*/
/*sunxi-dly-52M = <1 0 0 0 0>;*/
sunxi-dly-52M-ddr4 = <1 0 0 0 2>;
/*sunxi-dly-52M-ddr8 = <1 0 0 0 0>;*/
sunxi-dly-104M = <1 0 0 0 1>;
/*sunxi-dly-208M = <1 1 0 0 0>;*/
sunxi-dly-208M = <1 0 0 0 1>;
/*sunxi-dly-104M-ddr = <1 0 0 0 0>;*/
/*sunxi-dly-208M-ddr = <1 0 0 0 0>;*/
status = "okay";
/*status = "disabled";*/
};
pwm: pwm@0300a000 {
compatible = "allwinner,sunxi-pwm";
reg = <0x0 0x0300a000 0x0 0x3ff>;
clocks = <&clk_pwm>;
pwm-number = <8>;
pwm-base = <0x0>;
pwms = <&pwm0>, <&pwm1>, <&pwm2>, <&pwm3>, <&pwm4>,
<&pwm5>, <&pwm6>, <&pwm7>;
};
pwm0: pwm0@0300a000 {
compatible = "allwinner,sunxi-pwm0";
pinctrl-names = "active", "sleep";
pinctrl-0 = <&pwm0_pins_a>;
pinctrl-1 = <&pwm0_pins_b>;
reg_base = <0x0300a000>;
reg_peci_offset = <0x00>;
reg_peci_shift = <0x00>;
reg_peci_width = <0x01>;
reg_pis_offset = <0x04>;
reg_pis_shift = <0x00>;
reg_pis_width = <0x01>;
reg_crie_offset = <0x10>;
reg_crie_shift = <0x00>;
reg_crie_width = <0x01>;
reg_cfie_offset = <0x10>;
reg_cfie_shift = <0x01>;
reg_cfie_width = <0x01>;
reg_cris_offset = <0x14>;
reg_cris_shift = <0x00>;
reg_cris_width = <0x01>;
reg_cfis_offset = <0x14>;
reg_cfis_shift = <0x01>;
reg_cfis_width = <0x01>;
reg_clk_src_offset = <0x20>;
reg_clk_src_shift = <0x07>;
reg_clk_src_width = <0x02>;
reg_bypass_offset = <0x20>;
reg_bypass_shift = <0x05>;
reg_bypass_width = <0x01>;
reg_clk_gating_offset = <0x20>;
reg_clk_gating_shift = <0x04>;
reg_clk_gating_width = <0x01>;
reg_clk_div_m_offset = <0x20>;
reg_clk_div_m_shift = <0x00>;
reg_clk_div_m_width = <0x04>;
reg_pdzintv_offset = <0x30>;
reg_pdzintv_shift = <0x08>;
reg_pdzintv_width = <0x08>;
reg_dz_en_offset = <0x30>;
reg_dz_en_shift = <0x00>;
reg_dz_en_width = <0x01>;
reg_enable_offset = <0x40>;
reg_enable_shift = <0x00>;
reg_enable_width = <0x01>;
reg_cap_en_offset = <0x44>;
reg_cap_en_shift = <0x00>;
reg_cap_en_width = <0x01>;
reg_period_rdy_offset = <0x60>;
reg_period_rdy_shift = <0x0b>;
reg_period_rdy_width = <0x01>;
reg_pul_start_offset = <0x60>;
reg_pul_start_shift = <0x0a>;
reg_pul_start_width = <0x01>;
reg_mode_offset = <0x60>;
reg_mode_shift = <0x09>;
reg_mode_width = <0x01>;
reg_act_sta_offset = <0x60>;
reg_act_sta_shift = <0x08>;
reg_act_sta_width = <0x01>;
reg_prescal_offset = <0x60>;
reg_prescal_shift = <0x00>;
reg_prescal_width = <0x08>;
reg_entire_offset = <0x64>;
reg_entire_shift = <0x10>;
reg_entire_width = <0x10>;
reg_active_offset = <0x64>;
reg_active_shift = <0x00>;
reg_active_width = <0x10>;
};
pwm1: pwm1@0300a000 {
compatible = "allwinner,sunxi-pwm1";
pinctrl-names = "active", "sleep";
pinctrl-0 = <&pwm1_pins_a>;
pinctrl-1 = <&pwm1_pins_b>;
reg_base = <0x0300a000>;
reg_peci_offset = <0x00>;
reg_peci_shift = <0x01>;
reg_peci_width = <0x01>;
reg_pis_offset = <0x04>;
reg_pis_shift = <0x01>;
reg_pis_width = <0x01>;
reg_crie_offset = <0x10>;
reg_crie_shift = <0x02>;
reg_crie_width = <0x01>;
reg_cfie_offset = <0x10>;
reg_cfie_shift = <0x03>;
reg_cfie_width = <0x01>;
reg_cris_offset = <0x14>;
reg_cris_shift = <0x02>;
reg_cris_width = <0x01>;
reg_cfis_offset = <0x14>;
reg_cfis_shift = <0x03>;
reg_cfis_width = <0x01>;
reg_clk_src_offset = <0x20>;
reg_clk_src_shift = <0x07>;
reg_clk_src_width = <0x02>;
reg_bypass_offset = <0x20>;
reg_bypass_shift = <0x06>;
reg_bypass_width = <0x01>;
reg_clk_gating_offset = <0x20>;
reg_clk_gating_shift = <0x04>;
reg_clk_gating_width = <0x01>;
reg_clk_div_m_offset = <0x20>;
reg_clk_div_m_shift = <0x00>;
reg_clk_div_m_width = <0x04>;
reg_pdzintv_offset = <0x30>;
reg_pdzintv_shift = <0x08>;
reg_pdzintv_width = <0x08>;
reg_dz_en_offset = <0x30>;
reg_dz_en_shift = <0x00>;
reg_dz_en_width = <0x01>;
reg_enable_offset = <0x40>;
reg_enable_shift = <0x01>;
reg_enable_width = <0x01>;
reg_cap_en_offset = <0x44>;
reg_cap_en_shift = <0x01>;
reg_cap_en_width = <0x01>;
reg_period_rdy_offset = <0x80>;
reg_period_rdy_shift = <0x0b>;
reg_period_rdy_width = <0x01>;
reg_pul_start_offset = <0x80>;
reg_pul_start_shift = <0x0a>;
reg_pul_start_width = <0x01>;
reg_mode_offset = <0x80>;
reg_mode_shift = <0x09>;
reg_mode_width = <0x01>;
reg_act_sta_offset = <0x80>;
reg_act_sta_shift = <0x08>;
reg_act_sta_width = <0x01>;
reg_prescal_offset = <0x80>;
reg_prescal_shift = <0x00>;
reg_prescal_width = <0x08>;
reg_entire_offset = <0x84>;
reg_entire_shift = <0x10>;
reg_entire_width = <0x10>;
reg_active_offset = <0x84>;
reg_active_shift = <0x00>;
reg_active_width = <0x10>;
};
pwm2: pwm2@0300a000 {
compatible = "allwinner,sunxi-pwm2";
pinctrl-names = "active", "sleep";
pinctrl-0 = <&pwm2_pins_a>;
pinctrl-1 = <&pwm2_pins_b>;
reg_base = <0x0300a000>;
reg_peci_offset = <0x00>;
reg_peci_shift = <0x02>;
reg_peci_width = <0x01>;
reg_pis_offset = <0x04>;
reg_pis_shift = <0x02>;
reg_pis_width = <0x01>;
reg_crie_offset = <0x10>;
reg_crie_shift = <0x04>;
reg_crie_width = <0x01>;
reg_cfie_offset = <0x10>;
reg_cfie_shift = <0x05>;
reg_cfie_width = <0x01>;
reg_cris_offset = <0x14>;
reg_cris_shift = <0x04>;
reg_cris_width = <0x01>;
reg_cfis_offset = <0x14>;
reg_cfis_shift = <0x05>;
reg_cfis_width = <0x01>;
reg_clk_src_offset = <0x24>;
reg_clk_src_shift = <0x07>;
reg_clk_src_width = <0x02>;
reg_bypass_offset = <0x24>;
reg_bypass_shift = <0x06>;
reg_bypass_width = <0x01>;
reg_clk_gating_offset = <0x24>;
reg_clk_gating_shift = <0x04>;
reg_clk_gating_width = <0x01>;
reg_clk_div_m_offset = <0x24>;
reg_clk_div_m_shift = <0x00>;
reg_clk_div_m_width = <0x04>;
reg_pdzintv_offset = <0x34>;
reg_pdzintv_shift = <0x08>;
reg_pdzintv_width = <0x08>;
reg_dz_en_offset = <0x34>;
reg_dz_en_shift = <0x00>;
reg_dz_en_width = <0x01>;
reg_enable_offset = <0x40>;
reg_enable_shift = <0x02>;
reg_enable_width = <0x01>;
reg_cap_en_offset = <0x44>;
reg_cap_en_shift = <0x02>;
reg_cap_en_width = <0x01>;
reg_period_rdy_offset = <0xa0>;
reg_period_rdy_shift = <0x0b>;
reg_period_rdy_width = <0x01>;
reg_pul_start_offset = <0xa0>;
reg_pul_start_shift = <0x0a>;
reg_pul_start_width = <0x01>;
reg_mode_offset = <0xa0>;
reg_mode_shift = <0x09>;
reg_mode_width = <0x01>;
reg_act_sta_offset = <0xa0>;
reg_act_sta_shift = <0x08>;
reg_act_sta_width = <0x01>;
reg_prescal_offset = <0xa0>;
reg_prescal_shift = <0x00>;
reg_prescal_width = <0x08>;
reg_entire_offset = <0xa4>;
reg_entire_shift = <0x10>;
reg_entire_width = <0x10>;
reg_active_offset = <0xa4>;
reg_active_shift = <0x00>;
reg_active_width = <0x10>;
};
pwm3: pwm3@0300a000 {
compatible = "allwinner,sunxi-pwm3";
pinctrl-names = "active", "sleep";
pinctrl-0 = <&pwm3_pins_a>;
pinctrl-1 = <&pwm3_pins_b>;
reg_base = <0x0300a000>;
reg_peci_offset = <0x00>;
reg_peci_shift = <0x03>;
reg_peci_width = <0x01>;
reg_pis_offset = <0x04>;
reg_pis_shift = <0x04>;
reg_pis_width = <0x01>;
reg_crie_offset = <0x10>;
reg_crie_shift = <0x06>;
reg_crie_width = <0x01>;
reg_cfie_offset = <0x10>;
reg_cfie_shift = <0x07>;
reg_cfie_width = <0x01>;
reg_cris_offset = <0x14>;
reg_cris_shift = <0x06>;
reg_cris_width = <0x01>;
reg_cfis_offset = <0x14>;
reg_cfis_shift = <0x07>;
reg_cfis_width = <0x01>;
reg_clk_src_offset = <0x24>;
reg_clk_src_shift = <0x07>;
reg_clk_src_width = <0x02>;
reg_bypass_offset = <0x24>;
reg_bypass_shift = <0x06>;
reg_bypass_width = <0x01>;
reg_clk_gating_offset = <0x24>;
reg_clk_gating_shift = <0x04>;
reg_clk_gating_width = <0x01>;
reg_clk_div_m_offset = <0x24>;
reg_clk_div_m_shift = <0x00>;
reg_clk_div_m_width = <0x04>;
reg_pdzintv_offset = <0x34>;
reg_pdzintv_shift = <0x08>;
reg_pdzintv_width = <0x08>;
reg_dz_en_offset = <0x34>;
reg_dz_en_shift = <0x00>;
reg_dz_en_width = <0x01>;
reg_enable_offset = <0x40>;
reg_enable_shift = <0x03>;
reg_enable_width = <0x01>;
reg_cap_en_offset = <0x44>;
reg_cap_en_shift = <0x03>;
reg_cap_en_width = <0x01>;
reg_period_rdy_offset = <0xc0>;
reg_period_rdy_shift = <0x0b>;
reg_period_rdy_width = <0x01>;
reg_pul_start_offset = <0xc0>;
reg_pul_start_shift = <0x0a>;
reg_pul_start_width = <0x01>;
reg_mode_offset = <0xc0>;
reg_mode_shift = <0x09>;
reg_mode_width = <0x01>;
reg_act_sta_offset = <0xc0>;
reg_act_sta_shift = <0x08>;
reg_act_sta_width = <0x01>;
reg_prescal_offset = <0xc0>;
reg_prescal_shift = <0x00>;
reg_prescal_width = <0x08>;
reg_entire_offset = <0xc4>;
reg_entire_shift = <0x10>;
reg_entire_width = <0x10>;
reg_active_offset = <0xc4>;
reg_active_shift = <0x00>;
reg_active_width = <0x10>;
};
pwm4: pwm4@0300a000 {
compatible = "allwinner,sunxi-pwm4";
pinctrl-names = "active", "sleep";
pinctrl-0 = <&pwm4_pins_a>;
pinctrl-1 = <&pwm4_pins_b>;
reg_base = <0x0300a000>;
reg_peci_offset = <0x00>;
reg_peci_shift = <0x04>;
reg_peci_width = <0x01>;
reg_pis_offset = <0x04>;
reg_pis_shift = <0x04>;
reg_pis_width = <0x01>;
reg_crie_offset = <0x10>;
reg_crie_shift = <0x08>;
reg_crie_width = <0x01>;
reg_cfie_offset = <0x10>;
reg_cfie_shift = <0x09>;
reg_cfie_width = <0x01>;
reg_cris_offset = <0x14>;
reg_cris_shift = <0x08>;
reg_cris_width = <0x01>;
reg_cfis_offset = <0x14>;
reg_cfis_shift = <0x09>;
reg_cfis_width = <0x01>;
reg_clk_src_offset = <0x28>;
reg_clk_src_shift = <0x07>;
reg_clk_src_width = <0x02>;
reg_bypass_offset = <0x28>;
reg_bypass_shift = <0x06>;
reg_bypass_width = <0x01>;
reg_clk_gating_offset = <0x28>;
reg_clk_gating_shift = <0x04>;
reg_clk_gating_width = <0x01>;
reg_clk_div_m_offset = <0x28>;
reg_clk_div_m_shift = <0x00>;
reg_clk_div_m_width = <0x04>;
reg_pdzintv_offset = <0x38>;
reg_pdzintv_shift = <0x08>;
reg_pdzintv_width = <0x08>;
reg_dz_en_offset = <0x38>;
reg_dz_en_shift = <0x00>;
reg_dz_en_width = <0x01>;
reg_enable_offset = <0x40>;
reg_enable_shift = <0x04>;
reg_enable_width = <0x01>;
reg_cap_en_offset = <0x44>;
reg_cap_en_shift = <0x04>;
reg_cap_en_width = <0x01>;
reg_period_rdy_offset = <0xe0>;
reg_period_rdy_shift = <0x0b>;
reg_period_rdy_width = <0x01>;
reg_pul_start_offset = <0xe0>;
reg_pul_start_shift = <0x0a>;
reg_pul_start_width = <0x01>;
reg_mode_offset = <0xe0>;
reg_mode_shift = <0x09>;
reg_mode_width = <0x01>;
reg_act_sta_offset = <0xe0>;
reg_act_sta_shift = <0x08>;
reg_act_sta_width = <0x01>;
reg_prescal_offset = <0xe0>;
reg_prescal_shift = <0x00>;
reg_prescal_width = <0x08>;
reg_entire_offset = <0xe4>;
reg_entire_shift = <0x10>;
reg_entire_width = <0x10>;
reg_active_offset = <0xe4>;
reg_active_shift = <0x00>;
reg_active_width = <0x10>;
};
pwm5: pwm5@0300a000 {
compatible = "allwinner,sunxi-pwm5";
pinctrl-names = "active", "sleep";
pinctrl-0 = <&pwm5_pins_a>;
pinctrl-1 = <&pwm5_pins_b>;
reg_base = <0x0300a000>;
reg_peci_offset = <0x00>;
reg_peci_shift = <0x05>;
reg_peci_width = <0x01>;
reg_pis_offset = <0x04>;
reg_pis_shift = <0x05>;
reg_pis_width = <0x01>;
reg_crie_offset = <0x10>;
reg_crie_shift = <0x0a>;
reg_crie_width = <0x01>;
reg_cfie_offset = <0x10>;
reg_cfie_shift = <0x0b>;
reg_cfie_width = <0x01>;
reg_cris_offset = <0x14>;
reg_cris_shift = <0x0a>;
reg_cris_width = <0x01>;
reg_cfis_offset = <0x14>;
reg_cfis_shift = <0x0b>;
reg_cfis_width = <0x01>;
reg_clk_src_offset = <0x28>;
reg_clk_src_shift = <0x07>;
reg_clk_src_width = <0x02>;
reg_bypass_offset = <0x28>;
reg_bypass_shift = <0x06>;
reg_bypass_width = <0x01>;
reg_clk_gating_offset = <0x28>;
reg_clk_gating_shift = <0x04>;
reg_clk_gating_width = <0x01>;
reg_clk_div_m_offset = <0x28>;
reg_clk_div_m_shift = <0x00>;
reg_clk_div_m_width = <0x04>;
reg_pdzintv_offset = <0x38>;
reg_pdzintv_shift = <0x08>;
reg_pdzintv_width = <0x08>;
reg_dz_en_offset = <0x38>;
reg_dz_en_shift = <0x00>;
reg_dz_en_width = <0x01>;
reg_enable_offset = <0x40>;
reg_enable_shift = <0x05>;
reg_enable_width = <0x01>;
reg_cap_en_offset = <0x44>;
reg_cap_en_shift = <0x05>;
reg_cap_en_width = <0x01>;
reg_period_rdy_offset = <0x100>;
reg_period_rdy_shift = <0x0b>;
reg_period_rdy_width = <0x01>;
reg_pul_start_offset = <0x100>;
reg_pul_start_shift = <0x0a>;
reg_pul_start_width = <0x01>;
reg_mode_offset = <0x100>;
reg_mode_shift = <0x09>;
reg_mode_width = <0x01>;
reg_act_sta_offset = <0x100>;
reg_act_sta_shift = <0x08>;
reg_act_sta_width = <0x01>;
reg_prescal_offset = <0x100>;
reg_prescal_shift = <0x00>;
reg_prescal_width = <0x08>;
reg_entire_offset = <0x104>;
reg_entire_shift = <0x10>;
reg_entire_width = <0x10>;
reg_active_offset = <0x104>;
reg_active_shift = <0x00>;
reg_active_width = <0x10>;
};
pwm6: pwm6@0300a000 {
compatible = "allwinner,sunxi-pwm6";
pinctrl-names = "active", "sleep";
pinctrl-0 = <&pwm6_pins_a>;
pinctrl-1 = <&pwm6_pins_b>;
reg_base = <0x0300a000>;
reg_peci_offset = <0x00>;
reg_peci_shift = <0x06>;
reg_peci_width = <0x01>;
reg_pis_offset = <0x04>;
reg_pis_shift = <0x06>;
reg_pis_width = <0x01>;
reg_crie_offset = <0x10>;
reg_crie_shift = <0x0c>;
reg_crie_width = <0x01>;
reg_cfie_offset = <0x10>;
reg_cfie_shift = <0x0d>;
reg_cfie_width = <0x01>;
reg_cris_offset = <0x14>;
reg_cris_shift = <0x0c>;
reg_cris_width = <0x01>;
reg_cfis_offset = <0x14>;
reg_cfis_shift = <0x0d>;
reg_cfis_width = <0x01>;
reg_clk_src_offset = <0x2c>;
reg_clk_src_shift = <0x07>;
reg_clk_src_width = <0x02>;
reg_bypass_offset = <0x2c>;
reg_bypass_shift = <0x06>;
reg_bypass_width = <0x01>;
reg_clk_gating_offset = <0x2c>;
reg_clk_gating_shift = <0x04>;
reg_clk_gating_width = <0x01>;
reg_clk_div_m_offset = <0x2c>;
reg_clk_div_m_shift = <0x00>;
reg_clk_div_m_width = <0x04>;
reg_pdzintv_offset = <0x3c>;
reg_pdzintv_shift = <0x08>;
reg_pdzintv_width = <0x08>;
reg_dz_en_offset = <0x3c>;
reg_dz_en_shift = <0x00>;
reg_dz_en_width = <0x01>;
reg_enable_offset = <0x40>;
reg_enable_shift = <0x06>;
reg_enable_width = <0x01>;
reg_cap_en_offset = <0x44>;
reg_cap_en_shift = <0x06>;
reg_cap_en_width = <0x01>;
reg_period_rdy_offset = <0x120>;
reg_period_rdy_shift = <0x0b>;
reg_period_rdy_width = <0x01>;
reg_pul_start_offset = <0x120>;
reg_pul_start_shift = <0x0a>;
reg_pul_start_width = <0x01>;
reg_mode_offset = <0x120>;
reg_mode_shift = <0x09>;
reg_mode_width = <0x01>;
reg_act_sta_offset = <0x120>;
reg_act_sta_shift = <0x08>;
reg_act_sta_width = <0x01>;
reg_prescal_offset = <0x120>;
reg_prescal_shift = <0x00>;
reg_prescal_width = <0x08>;
reg_entire_offset = <0x124>;
reg_entire_shift = <0x10>;
reg_entire_width = <0x10>;
reg_active_offset = <0x124>;
reg_active_shift = <0x00>;
reg_active_width = <0x10>;
};
pwm7: pwm7@0300a000 {
compatible = "allwinner,sunxi-pwm7";
pinctrl-names = "active", "sleep";
pinctrl-0 = <&pwm7_pins_a>;
pinctrl-1 = <&pwm7_pins_b>;
reg_base = <0x0300a000>;
reg_peci_offset = <0x00>;
reg_peci_shift = <0x07>;
reg_peci_width = <0x01>;
reg_pis_offset = <0x04>;
reg_pis_shift = <0x07>;
reg_pis_width = <0x01>;
reg_crie_offset = <0x10>;
reg_crie_shift = <0x0e>;
reg_crie_width = <0x01>;
reg_cfie_offset = <0x10>;
reg_cfie_shift = <0x0f>;
reg_cfie_width = <0x01>;
reg_cris_offset = <0x14>;
reg_cris_shift = <0x0e>;
reg_cris_width = <0x01>;
reg_cfis_offset = <0x14>;
reg_cfis_shift = <0x0f>;
reg_cfis_width = <0x01>;
reg_clk_src_offset = <0x2c>;
reg_clk_src_shift = <0x07>;
reg_clk_src_width = <0x02>;
reg_bypass_offset = <0x2c>;
reg_bypass_shift = <0x06>;
reg_bypass_width = <0x01>;
reg_clk_gating_offset = <0x2c>;
reg_clk_gating_shift = <0x04>;
reg_clk_gating_width = <0x01>;
reg_clk_div_m_offset = <0x2c>;
reg_clk_div_m_shift = <0x00>;
reg_clk_div_m_width = <0x04>;
reg_pdzintv_offset = <0x3c>;
reg_pdzintv_shift = <0x08>;
reg_pdzintv_width = <0x08>;
reg_dz_en_offset = <0x3c>;
reg_dz_en_shift = <0x00>;
reg_dz_en_width = <0x01>;
reg_enable_offset = <0x40>;
reg_enable_shift = <0x07>;
reg_enable_width = <0x01>;
reg_cap_en_offset = <0x44>;
reg_cap_en_shift = <0x07>;
reg_cap_en_width = <0x01>;
reg_period_rdy_offset = <0x140>;
reg_period_rdy_shift = <0x0b>;
reg_period_rdy_width = <0x01>;
reg_pul_start_offset = <0x140>;
reg_pul_start_shift = <0x0a>;
reg_pul_start_width = <0x01>;
reg_mode_offset = <0x140>;
reg_mode_shift = <0x09>;
reg_mode_width = <0x01>;
reg_act_sta_offset = <0x140>;
reg_act_sta_shift = <0x08>;
reg_act_sta_width = <0x01>;
reg_prescal_offset = <0x140>;
reg_prescal_shift = <0x00>;
reg_prescal_width = <0x08>;
reg_entire_offset = <0x144>;
reg_entire_shift = <0x10>;
reg_entire_width = <0x10>;
reg_active_offset = <0x144>;
reg_active_shift = <0x00>;
reg_active_width = <0x10>;
};
boot_disp: boot_disp {
compatible = "allwinner,boot_disp";
};
lcdfb: lcdfb@0 {
compatible = "allwinner,sunxi-lcdfb";
pinctrl-names = "active","sleep";
status = "okay";
};
lcd_fb0: lcd_fb0@0 {
compatible = "allwinner,sunxi-lcd_fb0";
pinctrl-names = "active","sleep";
status = "okay";
};
ac200: ac200 {
compatible = "allwinner,sunxi-ac200";
/* clocks = <&clk_tcon0>; */
pinctrl-names = "active","sleep";
status = "okay";
};
vind0:vind@0 {
compatible = "allwinner,sunxi-vin-media", "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
device_id = <0>;
vind0_clk = <300000000>;
reg = <0x0 0x06600000 0x0 0x1000>;
clocks = <&clk_pll_periph0>, <&clk_hosc>, <&clk_pll_periph0>;
pinctrl-names = "mclk0-default","mclk0-sleep";
status = "okay";
isp0:isp@0 {
compatible = "allwinner,sunxi-isp";
reg = <0x0 0x02100000 0x0 0x800>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
device_id = <0>;
status = "okay";
};
scaler0:scaler@0 {
compatible = "allwinner,sunxi-scaler";
reg = <0x0 0x02101000 0x0 0x400>;
device_id = <0>;
status = "okay";
};
scaler1:scaler@1 {
compatible = "allwinner,sunxi-scaler";
reg = <0x0 0x02101400 0x0 0x400>;
device_id = <1>;
status = "okay";
};
actuator0:actuator@0 {
device_type = "actuator0";
compatible = "allwinner,sunxi-actuator";
actuator0_name = "ad5820_act";
actuator0_slave = <0x18>;
actuator0_af_pwdn = <>;
actuator0_afvdd = "afvcc-csi";
actuator0_afvdd_vol = <2800000>;
status = "disabled";
};
flash0:flash@0 {
device_type = "flash0";
compatible = "allwinner,sunxi-flash";
flash0_type = <2>;
flash0_en = <>;
flash0_mode = <>;
flash0_flvdd = "";
flash0_flvdd_vol = <>;
device_id = <0>;
status = "disabled";
};
sensor0:sensor@0 {
device_type = "sensor0";
sensor0_mname = "ov5640";
sensor0_twi_cci_id = <0>;
sensor0_twi_addr = <0x78>;
sensor0_pos = "rear";
sensor0_isp_used = <0>;
sensor0_fmt = <0>;
sensor0_stby_mode = <0>;
sensor0_vflip = <0>;
sensor0_hflip = <0>;
sensor0_iovdd = "iovdd-csi";
sensor0_iovdd_vol = <2800000>;
sensor0_avdd_vol = <2800000>;
sensor0_dvdd = "dvdd-csi-18";
sensor0_dvdd_vol = <1500000>;
sensor0_power_en = <>;
sensor0_reset = <&pio PE 14 1 0 1 0>;
sensor0_pwdn = <&pio PE 16 1 0 1 0>;
flash_handle = <&flash0>;
act_handle = <&actuator0>;
status = "okay";
};
sensor1:sensor@1 {
device_type = "sensor1";
sensor1_mname = "ov5647";
sensor1_twi_cci_id = <1>;
sensor1_twi_addr = <0x6c>;
sensor1_pos = "front";
sensor1_isp_used = <0>;
sensor1_fmt = <0>;
sensor1_stby_mode = <0>;
sensor1_vflip = <0>;
sensor1_hflip = <0>;
sensor1_iovdd = "iovdd-csi";
sensor1_iovdd_vol = <2800000>;
sensor1_avdd = "avdd-csi";
sensor1_avdd_vol = <2800000>;
sensor1_dvdd = "dvdd-csi-18";
sensor1_dvdd_vol = <1500000>;
sensor1_power_en = <>;
sensor1_reset = <&pio PE 14 1 0 1 0>;
sensor1_pwdn = <&pio PE 15 1 0 1 0>;
flash_handle = <>;
act_handle = <>;
status = "okay";
};
vinc0:vinc@0 {
device_type = "vinc0";
compatible = "allwinner,sunxi-vin-core";
reg = <0x0 0x06609000 0x0 0x200>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
vinc0_csi_sel = <3>;
vinc0_isp_sel = <0>;
vinc0_rear_sensor_sel = <0>;
vinc0_front_sensor_sel = <1>;
vinc0_sensor_list = <0>;
device_id = <0>;
status = "okay";
};
vinc1:vinc@1 {
device_type = "vinc1";
compatible = "allwinner,sunxi-vin-core";
reg = <0x0 0x06609200 0x0 0x200>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
vinc1_csi_sel = <3>;
vinc1_isp_sel = <0>;
vinc1_rear_sensor_sel = <0>;
vinc1_front_sensor_sel = <1>;
vinc1_sensor_list = <0>;
device_id = <1>;
status = "okay";
};
};
Vdevice: vdevice@0 {
compatible = "allwinner,sun8i-vdevice";
device_type = "Vdevice";
interrupt-parent = <&pio>;
interrupts = < PE 0 IRQ_TYPE_LEVEL_HIGH>; /* bank offset type */
pinctrl-names = "default";
pinctrl-0 = <&vdevice_pins_a>;
test-gpios = <&pio PE 0 1 2 2 1>;
status = "disable";
};
cryptoengine: ce@1904000 {
compatible = "allwinner,sunxi-ce";
device_name = "ce";
reg = <0x0 0x01904000 0x0 0xa0>,
<0x0 0x01904800 0x0 0xa0>; /* Unused */
interrupts = <GIC_SPI 65 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 66 IRQ_TYPE_EDGE_RISING>; /* Unused*/
clock-frequency = <300000000>; /* 300MHz */
clocks = <&clk_ce>, <&clk_pll_periph0x2>;
};
idc:idc@0x08130000{
compatible = "allwinner,sunxi-idc";
device_name = "idc";
reg = <0x0 0x08130000 0x0 0x338>;
irq_delay_en = <0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
irq_channel_array = <
0x0 0x0 0x0 0x0 0x0 0x0 0x0
0x0 0x0 0x0 0x0 0x0 0x0 0x0
0x0 0x0 0x0 0x0 0x0 0x0 0x0
0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
channel_delay_cycle = < 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0>;
wfi_check_en = <0x0>;
status = "okay";
};
nmi:nmi@0x01f00c00{
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sunxi-nmi";
reg = <0x0 0x01f00c00 0x0 0x50>;
nmi_irq_ctrl = <0x0c>;
nmi_irq_en = <0x40>;
nmi_irq_status = <0x10>;
nmi_irq_mask = <0x50>;
status = "okay";
};
nand0:nand0@04011000 {
compatible = "allwinner,sun8iw18-nand";
device_type = "nand0";
reg = <0x0 0x04011000 0x0 0x1000>; /* nand0 */
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_pll_periph1x2>,<&clk_nand0>,<&clk_nand1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&nand0_pins_a &nand0_pins_b>;
pinctrl-1 = <&nand0_pins_c>;
nand0_regulator1 = "vcc-nand";
nand0_regulator2 = "none";
nand0_cache_level = <0x55aaaa55>;
nand0_flush_cache_num = <0x55aaaa55>;
nand0_capacity_level = <0x55aaaa55>;
nand0_id_number_ctl = <0x55aaaa55>;
nand0_print_level = <0x55aaaa55>;
nand0_p0 = <0x55aaaa55>;
nand0_p1 = <0x55aaaa55>;
nand0_p2 = <0x55aaaa55>;
nand0_p3 = <0x55aaaa55>;
status = "disabled";
};
sunxi_thermal_sensor:thermal_sensor{
compatible = "allwinner,thermal_sensor";
reg = <0x0 0x05070400 0x0 0x100>;
interrupts = <GIC_SPI 49 IRQ_TYPE_NONE>;
clocks = <&clk_hosc>,<&clk_ths>;
sensor_num = <1>;
combine_num = <1>;
alarm_temp = <100000>;
shut_temp= <110000>;
status = "okay";
ths_combine0:ths_combine0{
compatible = "allwinner,ths_combine0";
#thermal-sensor-cells = <1>;
combine_sensor_num = <1>;
combine_sensor_type = "CPU";
combine_sensor_temp_type = "max";
combine_sensor_id = <0>;
};
};
cpu_budget_cooling:cpu_budget_cool{
compatible = "allwinner,budget_cooling";
#cooling-cells = <2>;
status = "okay";
state_cnt = <2>;
cluster_num = <1>;
state0 = <1512000 2>;
state1 = <720000 2>;
};
thermal-zones{
cpu_thermal_zone{
polling-delay-passive = <1000>;
polling-delay = <2000>;
thermal-sensors = <&ths_combine0 0>;
trips{
cpu_trip0:t0{
temperature = <100000>;
type = "passive";
hysteresis = <0>;
};
crt_trip:t1{
temperature = <110000>;
type = "critical";
hysteresis = <0>;
};
};
cooling-maps{
bind0{
contribution = <0>;
trip = <&cpu_trip0>;
cooling-device
= <&cpu_budget_cooling 1 1>;
};
};
};
};
gpadc:gpadc{
compatible = "allwinner,sunxi-gpadc";
reg = <0x0 0x05070000 0x0 0x400>;
interrupts = <GIC_SPI 48 IRQ_TYPE_NONE>;
clocks = <&clk_gpadc>;
status = "disable";
};
keyboard0:keyboard{
compatible = "allwinner,keyboard_1350mv";
reg = <0x0 0x05070800 0x0 0x400>;
interrupts = <GIC_SPI 50 IRQ_TYPE_NONE>;
status = "okay";
key_cnt = <5>;
key0 = <164 115>;
key1 = <415 114>;
key2 = <646 139>;
key3 = <900 28>;
key4 = <1157 102>;
wakeup-source;
};
cpucfg@09010000 {
compatible = "allwinner,sunxi-cpucfg";
reg = <0x0 0x09010000 0x0 0x400>;
};
cpuscfg@07000400 {
compatible = "allwinner,sunxi-cpuscfg";
cpu-soft-entry;
reg = <0x0 0x07000400 0x0 0x800>;
};
sysctl@03000000 {
compatible = "allwinner,sunxi-sysctl";
reg = <0x0 0x03000000 0x0 0x1000>;
};
ledc: ledc@0x06700000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sunxi-leds";
reg = <0x0 0x06700000 0x0 0x50>;
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ledcirq";
clocks = <&clk_ledc>, <&clk_cpuapb>;
clock-names = "clk_ledc", "clk_cpuapb";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&ledc_pins_a>;
pinctrl-1 = <&ledc_pins_b>;
led_count = <32>;
output_mode = "GRB";
reset_ns = <84>;
t1h_ns = <800>;
t1l_ns = <450>;
t0h_ns = <400>;
t0l_ns = <850>;
wait_time0_ns = <84>;
wait_time1_ns = <84>;
wait_data_time_ns = <600000>;
};
};
};
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