393 lines
14 KiB
C
393 lines
14 KiB
C
/*
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* spinand.c for SUNXI NAND .
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*
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* Copyright (C) 2016 Allwinner.
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*
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef _SUNXI_NAND_H
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#define _SUNXI_NAND_H
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#include <asm/types.h>
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#ifndef __s8
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typedef signed char __s8;
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#endif
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#ifndef __u8
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typedef unsigned char __u8;
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#endif
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#ifndef __s16
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typedef signed short __s16;
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#endif
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#ifndef __u16
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typedef unsigned short __u16;
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#endif
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#ifndef __s32
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typedef signed int __s32;
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#endif
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#ifndef __u32
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typedef unsigned int __u32;
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#endif
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#ifndef __s64
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typedef signed long long __s64;
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#endif
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#ifndef __u64
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typedef unsigned long long __u64;
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#endif
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#ifndef uchar
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typedef unsigned char uchar;
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#endif
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#ifndef uint16
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typedef unsigned short uint16;
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#endif
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#ifndef uint32
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typedef unsigned int uint32;
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#endif
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#ifndef uint
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typedef unsigned int uint;
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#endif
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#ifndef sint32
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typedef int sint32;
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#endif
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#ifndef uint64
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typedef unsigned long long uint64;
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#endif
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#ifndef sint16
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typedef short sint16;
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#endif
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#ifndef UINT8
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typedef unsigned char UINT8;
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#endif
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#ifndef UINT32
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typedef unsigned int UINT32;
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#endif
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#ifndef SINT32
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typedef signed int SINT32;
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#endif
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#define NULL ((void *)0)
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//extern __u32 SPIC_IO_BASE;
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/* run time control */
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#define TEST_SPI_NO (0)
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#define SPI_DEFAULT_CLK (40000000)
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#define SPI_TX_WL (32)
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#define SPI_RX_WL (32)
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#define SPI_FIFO_SIZE (64)
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#define SPI_CLK_SRC (1) //0-24M, 1-PLL6
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#define SPI_MCLK (40000000)
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//#define SPIC_BASE_OS (0x1000)
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extern void *NAND_GetIOBaseAddr(u32 no);
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#define SPI_BASE (u8 *)(NAND_GetIOBaseAddr(0))
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//#define SPI_BASE (0xe086f000)
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//#define SPI_IRQNO(_n) (INTC_SRC_SPI0 + (_n))
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#define SPI_VAR (SPI_BASE + 0x00)
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#define SPI_GCR (SPI_BASE + 0x04)
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#define SPI_TCR (SPI_BASE + 0x08)
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#define SPI_IER (SPI_BASE + 0x10)
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#define SPI_ISR (SPI_BASE + 0x14)
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#define SPI_FCR (SPI_BASE + 0x18)
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#define SPI_FSR (SPI_BASE + 0x1c)
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#define SPI_WCR (SPI_BASE + 0x20)
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#define SPI_CCR (SPI_BASE + 0x24)
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#define SPI_MBC (SPI_BASE + 0x30)
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#define SPI_MTC (SPI_BASE + 0x34)
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#define SPI_BCC (SPI_BASE + 0x38)
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#define SPI_TXD (SPI_BASE + 0x200)
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#define SPI_RXD (SPI_BASE + 0x300)
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/* bit field of registers */
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#define SPI_SOFT_RST (1U << 31)
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#define SPI_TXPAUSE_EN (1U << 7)
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#define SPI_MASTER (1U << 1)
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#define SPI_ENABLE (1U << 0)
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#define SPI_EXCHANGE (1U << 31)
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#define SPI_SAMPLE_MODE (1U << 13)
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#define SPI_LSB_MODE (1U << 12)
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#define SPI_SAMPLE_CTRL (1U << 11)
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#define SPI_RAPIDS_MODE (1U << 10)
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#define SPI_DUMMY_1 (1U << 9)
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#define SPI_DHB (1U << 8)
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#define SPI_SET_SS_1 (1U << 7)
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#define SPI_SS_MANUAL (1U << 6)
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#define SPI_SEL_SS0 (0U << 4)
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#define SPI_SEL_SS1 (1U << 4)
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#define SPI_SEL_SS2 (2U << 4)
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#define SPI_SEL_SS3 (3U << 4)
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#define SPI_SS_N_INBST (1U << 3)
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#define SPI_SS_ACTIVE0 (1U << 2)
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#define SPI_MODE0 (0U << 0)
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#define SPI_MODE1 (1U << 0)
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#define SPI_MODE2 (2U << 0)
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#define SPI_MODE3 (3U << 0)
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#define SPI_CPHA (1U << 0)
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#define SPI_SS_INT (1U << 13)
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#define SPI_TC_INT (1U << 12)
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#define SPI_TXUR_INT (1U << 11)
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#define SPI_TXOF_INT (1U << 10)
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#define SPI_RXUR_INT (1U << 9)
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#define SPI_RXOF_INT (1U << 8)
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#define SPI_TXFULL_INT (1U << 6)
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#define SPI_TXEMPT_INT (1U << 5)
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#define SPI_TXREQ_INT (1U << 4)
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#define SPI_RXFULL_INT (1U << 2)
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#define SPI_RXEMPT_INT (1U << 1)
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#define SPI_RXREQ_INT (1U << 0)
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#define SPI_ERROR_INT (SPI_TXUR_INT|SPI_TXOF_INT|SPI_RXUR_INT|SPI_RXOF_INT)
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#define SPI_TXFIFO_RST (1U << 31)
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#define SPI_TXFIFO_TST (1U << 30)
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#define SPI_TXDMAREQ_EN (1U << 24)
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#define SPI_RXFIFO_RST (1U << 15)
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#define SPI_RXFIFO_TST (1U << 14)
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#define SPI_RXDMAREQ_EN (1U << 8)
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#define SPI_MASTER_DUAL (1U << 28)
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#define SPI_NAND_READY (1U << 0)
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#define SPI_NAND_ERASE_FAIL (1U << 2)
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#define SPI_NAND_WRITE_FAIL (1U << 3)
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#define SPI_NAND_ECC_FIRST_BIT (4)
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#define SPI_NAND_ECC_BITMAP (0x3)
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#define SPI_NAND_INT_ECCSR_BITMAP (0xf)
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#define SPI_NAND_WREN 0x06
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#define SPI_NAND_WRDI 0x04
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#define SPI_NAND_GETSR 0x0f //get status/features
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#define SPI_NAND_SETSR 0x1f //set status/features
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#define SPI_NAND_PAGE_READ 0x13
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#define SPI_NAND_FAST_READ_X1 0x0b
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#define SPI_NAND_READ_X1 0x03
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#define SPI_NAND_READ_X2 0x3b
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#define SPI_NAND_READ_X4 0x6b
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#define SPI_NAND_READ_DUAL_IO 0xbb
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#define SPI_NAND_READ_QUAD_IO 0xeb
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#define SPI_NAND_RDID 0x9f
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#define SPI_NAND_PP 0x02
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#define SPI_NAND_PP_X4 0x32
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#define SPI_NAND_RANDOM_PP 0x84
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#define SPI_NAND_RANDOM_PP_X4 0x34
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#define SPI_NAND_PE 0x10 //program execute
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#define SPI_NAND_BE 0xd8 //block erase
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#define SPI_NAND_RESET 0xff
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#define SPI_NAND_READ_INT_ECCSTATUS 0x7c
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#undef readb
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#undef readw
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#undef writeb
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#undef writew
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#define readb(addr) (*((volatile unsigned char *)(addr)))
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#define readw(addr) (*((volatile unsigned int *)(addr)))
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#define writeb(v, addr) (*((volatile unsigned char *)(addr)) = (unsigned char)(v))
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#define writew(v, addr) (*((volatile unsigned int *)(addr)) = (unsigned int)(v))
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#define NAND_OP_TRUE (0) //define the successful return value
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#define NAND_OP_FALSE (-1) //define the failed return value
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//define the return value
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//#define ECC_CORRECT 9 //error can be corrected
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#define ECC_LIMIT 10 //reach the limit of the ability of ECC
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#define ERR_ECC 12 //too much ecc error
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#define ERR_NANDFAIL 13 //nand flash program or erase fail
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#define ERR_TIMEOUT 14 //hardware timeout
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#define SECTOR_SIZE 512 //the size of a sector, based on byte
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/* define the mask for the nand flash optional operation */
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/* nand flash support dual read operation */
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#define NAND_DUAL_READ (1 << 0)
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/* nand flash support page dual program operation */
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#define NAND_DUAL_PROGRAM (1 << 1)
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/* nand flash support multi-plane page read operation */
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#define NAND_MULTI_READ (1 << 2)
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/* nand flash support multi-plane page program operation */
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#define NAND_MULTI_PROGRAM (1 << 3)
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/* nand flash support external inter-leave operation, it based multi-chip */
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#define NAND_EXT_INTERLEAVE (1 << 4)
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/* nand flash support the maximum block erase cnt */
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#define NAND_MAX_BLK_ERASE_CNT (1 << 5)
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/* nand flash support to read reclaim Operation */
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#define NAND_READ_RECLAIM (1 << 6)
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/* nand flash need plane select for addr */
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#define NAND_TWO_PLANE_SELECT (1 << 7)
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#define SPINAND_TWO_PLANE_SELECT NAND_TWO_PLANE_SELECT
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/* nand flash need a dummy Byte after random fast read */
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#define NAND_ONEDUMMY_AFTER_RANDOMREAD (1 << 8)
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/* nand flash only support 8B user meta data under ecc protected */
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#define NAND_8B_METADATA_ECC_PROTECTED (1 << 9)
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/* nand flash support quad read operation */
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#define NAND_QUAD_READ (1<<10)
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/* nand flash support page quad program operation */
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#define NAND_QUAD_PROGRAM (1<<11)
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/* nand flash should not enable QE register bit manually */
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#define SPINAND_QUAD_NO_NEED_ENABLE (1 << 12)
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enum ecc_status_shift {
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ECC_STATUS_SHIFT_0 = 0,
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ECC_STATUS_SHIFT_1,
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ECC_STATUS_SHIFT_2,
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ECC_STATUS_SHIFT_3,
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ECC_STATUS_SHIFT_4,
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ECC_STATUS_SHIFT_5,
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ECC_STATUS_SHIFT_6,
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ECC_STATUS_SHIFT_7,
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};
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//define the nand flash physical information parameter type, for id table
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struct __NandPhyInfoPar_t {
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__u8 NandID[8]; //the ID number of the nand flash chip
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__u8 DieCntPerChip; //the count of the Die in one nand flash chip
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__u8 SectCntPerPage; //the count of the sectors in one single physical page
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__u16 PageCntPerBlk; //the count of the pages in one single physical block
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__u16 BlkCntPerDie; //the count fo the physical blocks in one nand flash Die
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__u32 OperationOpt; //the bitmap that marks which optional operation that the nand flash can support
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__u16 AccessFreq; //the highest access frequence of the nand flash chip, based on MHz
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__u32 SpiMode; //spi nand mode, 0:mode 0, 3:mode 3
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__u32 pagewithbadflag; //bad block flag was written at the first byte of spare area of this page
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struct spi_nand_function *spi_nand_function; //erase,write,read function for spi nand
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__u32 MultiPlaneBlockOffset; //the value of the block number offset between the two plane block
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__u32 MaxEraseTimes; //the max erase times of a physic block
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__u32 MaxEccBits; //the max ecc bits that nand support
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__u32 EccLimitBits; //the ecc limit flag for tne nand
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__u32 Idnumber;
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__u32 EccType; // Just use in spinand2, select different ecc status type.
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__u32 EccProtectedType; // just use in spinand2, select different ecc protected type.
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enum ecc_status_shift ecc_status_shift;
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__u8 reserved[4]; //reserved for 32bit align
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};
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//define the nand flash storage system information
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struct __NandStorageInfo_t {
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__u8 ChipCnt; //the count of the total nand flash chips are currently connecting on the CE pin
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__u16 ChipConnectInfo; //chip connect information, bit == 1 means there is a chip connecting on the CE pin
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__u8 ConnectMode; //the rb connect mode
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__u8 BankCntPerChip; //the count of the banks in one nand chip, multiple banks can support Inter-Leave
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__u8 DieCntPerChip; //the count of the dies in one nand chip, block management is based on Die
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__u8 PlaneCntPerDie; //the count of planes in one die, multiple planes can support multi-plane operation
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__u8 SectorCntPerPage; //the count of sectors in one single physic page, one sector is 0.5k
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__u16 PageCntPerPhyBlk; //the count of physic pages in one physic block
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__u32 BlkCntPerDie; //the count of the physic blocks in one die, include valid block and invalid block
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__u32 OperationOpt; //the mask of the operation types which current nand flash can support support
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__u16 FrequencePar; //the parameter of the hardware access clock, based on 'MHz'
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__u32 SpiMode; //spi nand mode, 0:mode 0, 3:mode 3
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__u8 NandChipId[8]; //the nand chip id of current connecting nand chip
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__u32 pagewithbadflag; //bad block flag was written at the first byte of spare area of this page
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__u32 MultiPlaneBlockOffset; //the value of the block number offset between the two plane block
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__u32 MaxEraseTimes; //the max erase times of a physic block
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__u32 MaxEccBits; //the max ecc bits that nand support
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__u32 EccLimitBits; //the ecc limit flag for tne nand
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__u32 Idnumber;
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__u32 EccType; // Just use in spinand2, select different ecc status type.
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__u32 EccProtectedType; // just use in spinand2, select different ecc protected type.
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struct spi_nand_function *spi_nand_function; //erase,write,read function for spi nand
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enum ecc_status_shift ecc_status_shift;
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};
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//define the page buffer pool for nand flash driver
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struct __NandPageCachePool_t {
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__u8 *PageCache0; //the pointer to the first page size ram buffer
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// __u8 *PageCache1; //the pointer to the second page size ram buffer
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// __u8 *PageCache2; //the pointer to the third page size ram buffer
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__u8 *SpareCache;
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__u8 *TmpPageCache;
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__u8 *SpiPageCache;
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__u8 *SpareCache1;
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};
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struct boot_physical_param {
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__u32 chip; //chip no
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__u32 block; // block no within chip
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__u32 page; // apge no within block
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__u32 sectorbitmap;
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void *mainbuf; //data buf
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void *oobbuf; //oob buf
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};
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struct spi_nand_function {
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__s32 (*spi_nand_reset)(__u32 spi_no, __u32 chip);
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__s32 (*spi_nand_read_status)(__u32 spi_no, __u32 chip, __u8 status, __u32 mode);
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__s32 (*spi_nand_setstatus)(__u32 spi_no, __u32 chip, __u8 reg);
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__s32 (*spi_nand_getblocklock)(__u32 spi_no, __u32 chip, __u8 *reg);
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__s32 (*spi_nand_setblocklock)(__u32 spi_no, __u32 chip, __u8 reg);
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__s32 (*spi_nand_getotp)(__u32 spi_no, __u32 chip, __u8 *reg);
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__s32 (*spi_nand_setotp)(__u32 spi_no, __u32 chip, __u8 reg);
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__s32 (*spi_nand_getoutdriver)(__u32 spi_no, __u32 chip, __u8 *reg);
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__s32 (*spi_nand_setoutdriver)(__u32 spi_no, __u32 chip, __u8 reg);
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__s32 (*erase_single_block)(struct boot_physical_param *eraseop);
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__s32 (*write_single_page)(struct boot_physical_param *writeop);
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__s32 (*read_single_page)(struct boot_physical_param *readop, __u32 spare_only_flag);
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};
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extern struct spi_nand_function spinand_function;
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extern int nand_dma_config_start(__u32 tx_mode, __u32 addr, __u32 length);
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extern int NAND_WaitDmaFinish(__u32 tx_flag, __u32 rx_flag);
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extern int Nand_Dma_End(__u32 rw, __u32 addr, __u32 length);
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extern int spinand_get_mbr(char *buffer, uint len);
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extern int spinand_uboot_init(int boot_mode);
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extern int spinand_uboot_exit(int force);
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extern int spinand_uboot_probe(void);
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extern uint spinand_uboot_read(uint start, uint sectors, void *buffer);
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extern uint spinand_uboot_write(uint start, uint sectors, void *buffer);
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extern int spinand_download_boot0(uint length, void *buffer);
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extern int spinand_download_uboot(uint length, void *buffer);
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extern int spinand_force_download_uboot(uint length, void *buffer);
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extern int spinand_uboot_erase(int user_erase);
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extern uint spinand_uboot_get_flash_info(void *buffer, uint length);
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extern uint spinand_uboot_set_flash_info(void *buffer, uint length);
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extern uint spinand_uboot_get_flash_size(void);
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extern int spinand_uboot_flush(void);
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extern int SPINAND_Uboot_Force_Erase(void);
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uint spinand_upload_boot0(uint length, void *buf);
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int spinand_download_boot0_simple(uint length, void *buffer);
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#endif
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