132 lines
3.9 KiB
C
132 lines
3.9 KiB
C
/*
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*
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* include/linux/dma/sunxi/dma-sun50iw9.h
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*
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* Copyright (C) 2017 Allwinner.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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*/
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#ifndef __DMA_SUN50IW10__
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#define __DMA_SUN50IW10__
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/*
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* The source DRQ type and port corresponding relation
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*/
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#define DRQSRC_SRAM 0
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#define DRQSRC_SDRAM 0 /* DRQDST_DRAM = 1 ? */
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#define DRQSRC_SPDIFRX 2
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#define DRQSRC_DAUDIO_0_RX 3
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#define DRQSRC_DAI0_RX DRQSRC_DAUDIO_0_RX
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#define DRQSRC_DAUDIO_1_RX 4
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#define DRQSRC_DAI1_RX DRQSRC_DAUDIO_1_RX
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#define DRQSRC_DAUDIO_2_RX 5
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#define DRQSRC_DAI2_RX DRQSRC_DAUDIO_2_RX
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#define DRQSRC_DAUDIO_3_RX 6
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#define DRQSRC_DAI3_RX DRQSRC_DAUDIO_3_RX
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#define DRQSRC_AUDIO_CODEC 7
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#define DRQSRC_DMIC 8
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/* #define DRQSRC_RESERVE 8 */
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/* #define DRQSRC_RESERVE 9 */
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#define DRQSRC_NAND0 10
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/* #define DRQSRC_RESERVE 11 */
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#define DRQSRC_GPADC 12
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/* #define DRQSRC_RESERVE 13 */
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#define DRQSRC_UART0_RX 14
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#define DRQSRC_UART1_RX 15
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#define DRQSRC_UART2_RX 16
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#define DRQSRC_UART3_RX 17
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#define DRQSRC_UART4_RX 18
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#define DRQSRC_UART5_RX 19
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#define DRQSRC_UART6_RX 20
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/* #define DRQSRC_RESERVE 20 */
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/* #define DRQSRC_RESERVE 21 */
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#define DRQSRC_SPI0_RX 22
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#define DRQSRC_SPI1_RX 23
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#define DRQSRC_SPI2_RX 24
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/* #define DRQSRC_RESERVE 24 */
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/* #define DRQSRC_RESERVE 25 */
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/* #define DRQSRC_RESERVE 26 */
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/* #define DRQSRC_RESERVE 27 */
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/* #define DRQSRC_RESERVE 28 */
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/* #define DRQSRC_RESERVE 29 */
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#define DRQSRC_OTG_EP1 30
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#define DRQSRC_OTG_EP2 31
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#define DRQSRC_OTG_EP3 32
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#define DRQSRC_OTG_EP4 33
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#define DRQSRC_OTG_EP5 34
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/* reserved: 35~39 */
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#define DRQSRC_R_UART_RX 40
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/* reserved: 41~42 */
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#define DRQSRC_TWI0_RX 43
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#define DRQSRC_TWI1_RX 44
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#define DRQSRC_TWI2_RX 45
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#define DRQSRC_TWI3_RX 46
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#define DRQSRC_TWI4_RX 47
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#define DRQSRC_TWI5_RX 48
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#define DRQSRC_R_TWI0 50 /* new */
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#define DRQSRC_R_TWI1 51 /* new */
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/*
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* The destination DRQ type and port corresponding relation
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*/
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#define DRQDST_SRAM 0
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#define DRQDST_SDRAM 0 /* DRQDST_DRAM = 1 ? */
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#define DRQDST_SPDIFTX 2
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#define DRQDST_DAUDIO_0_TX 3
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#define DRQDST_DAI0_TX DRQDST_DAUDIO_0_TX
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#define DRQDST_DAUDIO_1_TX 4
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#define DRQDST_DAI1_TX DRQDST_DAUDIO_1_TX
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#define DRQDST_DAUDIO_2_TX 5
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#define DRQDST_DAI2_TX DRQDST_DAUDIO_2_TX
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#define DRQDST_DAUDIO_3_TX 6
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#define DRQDST_DAI3_TX DRQDST_DAUDIO_3_TX
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#define DRQDST_AUDIO_CODEC 7
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/* #define DRQDST_RESERVE 7 */
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/* #define DRQDST_RESERVE 8 */
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/* #define DRQDST_RESERVE 9 */
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#define DRQDST_NAND0 10
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#define DRQDST_LEDC 11
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/* #define DRQDST_RESERVE 12 */
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#define DRQDST_IR_TX 13
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#define DRQDST_UART0_TX 14
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#define DRQDST_UART1_TX 15
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#define DRQDST_UART2_TX 16
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#define DRQDST_UART3_TX 17
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#define DRQDST_UART4_TX 18
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#define DRQDST_UART5_TX 19
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#define DRQDST_UART6_TX 20
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/* #define DRQDST_RESERVE 20 */
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/* #define DRQDST_RESERVE 21 */
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#define DRQDST_SPI0_TX 22
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#define DRQDST_SPI1_TX 23
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#define DRQDST_SPI2_TX 24
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/* #define DRQDST_RESERVE 24 */
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/* #define DRQDST_RESERVE 25 */
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/* #define DRQDST_RESERVE 26 */
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/* #define DRQDST_RESERVE 27 */
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/* #define DRQDST_RESERVE 28 */
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/* #define DRQDST_RESERVE 29 */
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#define DRQDST_OTG_EP1 30
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#define DRQDST_OTG_EP2 31
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#define DRQDST_OTG_EP3 32
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#define DRQDST_OTG_EP4 33
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#define DRQDST_OTG_EP5 34
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/* reserved: 35~39 */
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#define DRQDST_R_UART_TX 40
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/* reserved: 41~42 */
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#define DRQDST_TWI0_TX 43
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#define DRQDST_TWI1_TX 44
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#define DRQDST_TWI2_TX 45
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#define DRQDST_TWI3_TX 46
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#define DRQDST_TWI4_TX 47
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#define DRQDST_TWI5_TX 48
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#define DRQDST_R_TWI0 50 /* new */
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#define DRQDST_R_TWI1 51 /* new */
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#endif /*__DMA_SUN50IW10__ */
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