128 lines
3.6 KiB
C
128 lines
3.6 KiB
C
/*
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*
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* include/linux/dma/sunxi/dma-sun50iw11.h
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*
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* Copyright (C) 2017 Allwinner.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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*/
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#ifndef __DMA_SUN50IW11__
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#define __DMA_SUN50IW11__
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/*
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* The source DRQ type and port corresponding relation
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*/
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#define DRQSRC_SRAM 0
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#define DRQSRC_SDRAM 0
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#define DRQSRC_SPDIFRX 2
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#define DRQSRC_DAUDIO_0_RX 3
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#define DRQSRC_DAUDIO_1_RX 4
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#define DRQSRC_DAUDIO_2_RX 5
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#define DRQSRC_R_AUDIO_CODEC 6
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#define DRQSRC_R_DMIC 7
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/* #define DRQSRC_RESERVE 8 */
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#define DRQSRC_CE 9
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#define DRQSRC_NAND 10
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/* #define DRQSRC_RESERVE 11 */
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#define DRQSRC_R_GPADC 12
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/* #define DRQSRC_RESERVE 13 */
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#define DRQSRC_UART0_RX 14
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#define DRQSRC_UART1_RX 15
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#define DRQSRC_UART2_RX 16
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#define DRQSRC_UART3_RX 17
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/* #define DRQSRC_RESERVE 18 */
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/* #define DRQSRC_RESERVE 19 */
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/* #define DRQSRC_RESERVE 20 */
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/* #define DRQSRC_RESERVE 21 */
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#define DRQSRC_SPI0_RX 22
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#define DRQSRC_SPI1_RX 23
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/* #define DRQSRC_RESERVE 24 */
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/* #define DRQSRC_RESERVE 25 */
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/* #define DRQSRC_RESERVE 26 */
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/* #define DRQSRC_RESERVE 27 */
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/* #define DRQSRC_RESERVE 28 */
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/* #define DRQSRC_RESERVE 29 */
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#define DRQSRC_OTG0_EP1 30
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#define DRQSRC_OTG0_EP2 31
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#define DRQSRC_OTG0_EP3 32
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#define DRQSRC_OTG0_EP4 33
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#define DRQSRC_OTG0_EP5 34
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#define DRQSRC_OTG_EP1 DRQSRC_OTG0_EP1
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#define DRQSRC_OTG_EP2 DRQSRC_OTG0_EP2
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#define DRQSRC_OTG_EP3 DRQSRC_OTG0_EP3
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#define DRQSRC_OTG_EP4 DRQSRC_OTG0_EP4
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#define DRQSRC_OTG_EP5 DRQSRC_OTG0_EP5
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#define DRQSRC_OTG1_EP1 35
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#define DRQSRC_OTG1_EP2 36
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#define DRQSRC_OTG1_EP3 37
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#define DRQSRC_OTG1_EP4 38
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#define DRQSRC_OTG1_EP5 39
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/* reserved: 40~42 */
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#define DRQSRC_TWI0_RX 43
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#define DRQSRC_TWI1_RX 44
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/* reserved: 45~47 */
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#define DRQSRC_R_MAD 48
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#define DRQSRC_R_TWI0 49 /* new */
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#define DRQSRC_R_UART0 50 /* new */
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#define DRQSRC_R_DAUDIO_0_RX 51 /* new */
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#define DRQSRC_R_DAUDIO_1_RX 52 /* new */
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#define DRQSRC_R_PSRAM 53 /* new */
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/*
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* The destination DRQ type and port corresponding relation
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*/
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#define DRQDST_SRAM 0
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#define DRQDST_SDRAM 0
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#define DRQDST_SPDIFTX 2
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#define DRQDST_DAUDIO_0_TX 3
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#define DRQDST_DAUDIO_1_TX 4
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#define DRQDST_DAUDIO_2_TX 5
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#define DRQDST_R_AUDIO_CODEC 6
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#define DRQDST_R_DMIC 7
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/* #define DRQDST_RESERVE 8 */
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#define DRQDST_CE 9
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#define DRQDST_NAND0 10
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/* reserved: 11~12 */
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#define DRQDST_IR_TX 13
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#define DRQDST_UART0_TX 14
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#define DRQDST_UART1_TX 15
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#define DRQDST_UART2_TX 16
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#define DRQDST_UART3_TX 17
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/* reserved: 18~21 */
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#define DRQDST_SPI0_TX 22
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#define DRQDST_SPI1_TX 23
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/* reserved: 24~29 */
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#define DRQDST_OTG0_EP1 30
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#define DRQDST_OTG0_EP2 31
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#define DRQDST_OTG0_EP3 32
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#define DRQDST_OTG0_EP4 33
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#define DRQDST_OTG0_EP5 34
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#define DRQDST_OTG_EP1 DRQDST_OTG0_EP1
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#define DRQDST_OTG_EP2 DRQDST_OTG0_EP2
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#define DRQDST_OTG_EP3 DRQDST_OTG0_EP3
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#define DRQDST_OTG_EP4 DRQDST_OTG0_EP4
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#define DRQDST_OTG_EP5 DRQDST_OTG0_EP5
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#define DRQDST_OTG1_EP1 35
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#define DRQDST_OTG1_EP2 36
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#define DRQDST_OTG1_EP3 37
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#define DRQDST_OTG1_EP4 38
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#define DRQDST_OTG1_EP5 39
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/* reserved: 40~41 */
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#define DRQDST_LEDC 42
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#define DRQDST_TWI0_TX 43
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#define DRQDST_TWI1_TX 44
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/* reserved: 45~47 */
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#define DRQDST_R_MAD 48
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#define DRQDST_R_TWI0 49 /* new */
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#define DRQDST_R_UART0 50 /* new */
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#define DRQDST_R_DAUDIO_0_TX 51 /* new */
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#define DRQDST_R_DAUDIO_1_TX 52 /* new */
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#define DRQDST_R_PSRAM 53 /* new */
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#endif /*__DMA_SUN50IW11__ */
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