135 lines
3.5 KiB
C
135 lines
3.5 KiB
C
/*
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* dspo_drv.h
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*
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* Copyright (c) 2007-2021 Allwinnertech Co., Ltd.
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* Author: zhengxiaobin <zhengxiaobin@allwinnertech.com>
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*
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef _DSPO_DRV_H
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#define _DSPO_DRV_H
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#include <linux/types.h>
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#include <linux/ioctl.h>
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enum dspo_output_mode {
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DSPO_MOD_NTSC = 0,
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DSPO_MOD_PAL = 1,
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DSPO_MOD_720X480I_60 = 2,
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DSPO_MOD_720X576I_60 = 3,
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DSPO_MOD_720X480P_60 = 4,
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DSPO_MOD_720X576P_50 = 5,
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DSPO_MOD_1280X720P_25 = 6,
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DSPO_MOD_1280X720P_50 = 7,
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DSPO_MOD_1280X720P_60 = 8,
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DSPO_MOD_1920X1080I_50 = 9,
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DSPO_MOD_1920X1080I_60 = 10,
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DSPO_MOD_1920X1080P_50 = 11,
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DSPO_MOD_1920X1080P_60 = 12,
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DSPO_MOD_3840X1080P_30 = 13,
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DSPO_CUSTOM_MODE = 14,//do not change this value
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};
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enum dspo_protocol_t {
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DSPO_BT1120,
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DSPO_BT656,
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};
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enum dspo_datawidth_t {
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DSPO_8_BIT,
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DSPO_16_BIT,
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};
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enum dspo_data_seq_t {
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DSPO_CB_Y_CR_Y,
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DSPO_CR_Y_CB_Y,
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DSPO_Y_CB_Y_CR,
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DSPO_Y_CR_Y_CB,
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};
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struct dspo_video_timings {
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enum dspo_output_mode tv_mode;
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__u32 pixel_clk;
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__u32 pixel_repeat; /* pixel repeat (pixel_repeat+1) times */
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__u32 x_res;
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__u32 y_res;
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__u32 hor_total_time;
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__u32 hor_back_porch;
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__u32 hor_front_porch;
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__u32 hor_sync_time;
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__u32 ver_total_time;
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__u32 ver_back_porch;
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__u32 ver_front_porch;
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__u32 ver_sync_time;
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__u32 hor_sync_polarity; /* 0: negative, 1: positive */
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__u32 ver_sync_polarity; /* 0: negative, 1: positive */
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bool b_interlace;
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__u32 vactive_space;
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__u32 trd_mode;
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};
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struct dspo_dclk_adjust_t {
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bool dclk_en;
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bool dclk_invt;
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__u32 dclk_dly_num;
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};
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struct dspo_config_t {
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enum dspo_protocol_t protocol;
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enum dspo_datawidth_t bit_width;
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bool separate_sync;
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enum dspo_data_seq_t data_seq_sel;
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struct dspo_dclk_adjust_t dclk_set;
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enum dspo_output_mode output_mode;
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struct dspo_video_timings timing_info;
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};
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enum dspo_infmt_t {
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DSPO_FORMAT_ARGB888 = 0,
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DSPO_FORMAT_YUV444 = 0x1,
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DSPO_FORMAT_YUV422_I_VYUY = 0x4, /* MSB V0-Y1-U0-Y0 LSB */
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DSPO_FORMAT_YUV422_I_YVYU = 0x5, /* MSB Y1-V0-Y0-U0 LSB */
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DSPO_FORMAT_YUV422_I_UYVY = 0x6, /* MSB U0-Y1-V0-Y0 LSB */
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DSPO_FORMAT_YUV422_I_YUYV = 0x7, /* MSB Y1-U0-Y0-V0 LSB */
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DSPO_FORMAT_YUV422_SP_UVUV = 0x8, /* MSB V1-U1-V0-U0 LSB */
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DSPO_FORMAT_YUV422_SP_VUVU = 0xa, /* MSB U1-V1-U0-V0 LSB */
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DSPO_FORMAT_YUV420_SP_UVUV = 0xc, /* MSB V1-U1-V0-U0 LSB */
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DSPO_FORMAT_YUV420_SP_VUVU = 0xe, /* MSB U1-V1-U0-V0 LSB */
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DSPO_FORMAT_INVALID,
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};
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struct dspo_dma_info_t {
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enum dspo_infmt_t fmt;
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__u32 height;
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__u32 width;
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int fd;
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unsigned long long addr[2];
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bool use_phy_addr;
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};
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#define SUNXI_DSPO_IOC_MAGIC 'P'
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//#define SUNXI_G2D_IO(nr) _IO(SUNXI_G2D_IOC_MAGIC, nr)
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//#define SUNXI_G2D_IOR(nr, size) _IOR(SUNXI_G2D_IOC_MAGIC, nr, size)
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//#define SUNXI_G2D_IOW(nr, size) _IOW(SUNXI_G2D_IOC_MAGIC, nr, size)
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//#define SUNXI_G2D_IOWR(nr, size) _IOWR(SUNXI_G2D_IOC_MAGIC, nr, size)
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//definition of dspo ioctl command
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#define DSPO_CMD_DEVICE_SWITCH _IOW(SUNXI_DSPO_IOC_MAGIC, 0x01, struct dspo_config_t)
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#define DSPO_CMD_COMMIT _IOW(SUNXI_DSPO_IOC_MAGIC, 0x02, struct dspo_dma_info_t)
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//#define DSPO_CMD_DESC_COMMIT _IOW(SUNXI_DSPO_IOC_MAGIC, 0x03, struct dspo_config_t)
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#endif /*End of file*/
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