313 lines
7.2 KiB
C
313 lines
7.2 KiB
C
/*
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* sound\soc\sunxi\sun50iw11\sunxi-spdif.h
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* (C) Copyright 2019-2025
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* allwinnertech Technology Co., Ltd. <www.allwinnertech.com>
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* yumingfeng <yumingfeng@allwinnertech.com>
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*
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* some simple description for this code
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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*/
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#ifndef __SUNXI_SPDIF_H_
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#define __SUNXI_SPDIF_H_
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#include "sunxi-pcm.h"
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/* SPDIF register definition */
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#define SUNXI_SPDIF_CTL 0x00
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#define SUNXI_SPDIF_TXCFG 0x04
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#define SUNXI_SPDIF_RXCFG 0x08
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#define SUNXI_SPDIF_INT_STA (0x0C)
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#define SUNXI_SPDIF_RXFIFO 0x10
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#define SUNXI_SPDIF_FIFO_CTL 0x14
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#define SUNXI_SPDIF_FIFO_STA 0x18
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#define SUNXI_SPDIF_INT 0x1C
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#define SUNXI_SPDIF_TXFIFO (0x20)
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#define SUNXI_SPDIF_TXCNT 0x24
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#define SUNXI_SPDIF_RXCNT 0x28
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#define SUNXI_SPDIF_TXCH_STA0 0x2C
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#define SUNXI_SPDIF_TXCH_STA1 0x30
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#define SUNXI_SPDIF_RXCH_STA0 0x34
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#define SUNXI_SPDIF_RXCH_STA1 0x38
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#if IS_ENABLED(CONFIG_SND_SUNXI_SOC_SUN50IW11_SPDIF_RX_IEC61937)
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#define SUNXI_SPDIF_EXP_CTL 0x40
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#define SUNXI_SPDIF_EXP_ISTA 0x44
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#define SUNXI_SPDIF_EXP_INFO0 0x48
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#define SUNXI_SPDIF_EXP_INFO1 0x4C
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#define SUNXI_SPDIF_EXP_DBG0 0x50
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#define SUNXI_SPDIF_EXP_DBG1 0x54
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#define SUNXI_SPDIF_EXP_VER 0x58
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#endif
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#if IS_ENABLED(CONFIG_SND_SUNXI_SOC_SUN50IW11_SPDIF_RX_IEC61937)
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#define SUNXI_SPDIF_REG_MAX SUNXI_SPDIF_EXP_VER
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#else
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#define SUNXI_SPDIF_REG_MAX SUNXI_SPDIF_RXCH_STA1
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#endif
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/* SUNXI_SPDIF_CTL register */
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#define CTL_RESET 0
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#define CTL_GEN_EN 1
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#define CTL_LOOP_EN 2
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#define CTL_RESET_RX 0
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/* SUNXI_SPDIF_TXCFG register */
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#define TXCFG_TXEN 0
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/* Chan status generated form TX_CHSTA */
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#define TXCFG_CHAN_STA_EN 1
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#define TXCFG_SAMPLE_BIT 2
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#define TXCFG_CLK_DIV_RATIO 4
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#define TXCFG_DATA_TYPE 16
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/* Only valid in PCM mode */
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#define TXCFG_ASS 17
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#define TXCFG_SINGLE_MOD 31
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/* SUNXI_SPDIF_RXCFG register */
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#define RXCFG_RXEN 0
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#define RXCFG_CHSR_CP 1
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#define RXCFG_CHST_SRC 3
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#define RXCFG_LOCK_FLAG 4
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/* SUNXI_SPDIF_FIFO_CTL register */
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#define FIFO_CTL_RXOM 0
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#define FIFO_CTL_TXIM 2
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#define FIFO_CTL_RXTL 4
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#define FIFO_CTL_TXTL 12
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#define FIFO_CTL_FRX 29
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#define FIFO_CTL_FTX 30
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#define FIFO_CTL_HUBEN 31
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#define CTL_TXTL_MASK 0xFF
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#define CTL_TXTL_DEFAULT 0x40
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#define CTL_RXTL_MASK 0x7F
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#define CTL_RXTL_DEFAULT 0x20
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/* SUNXI_SPDIF_FIFO_STA register */
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#define FIFO_STA_RXA_CNT 0
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#define FIFO_STA_RXA 15
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#define FIFO_STA_TXA_CNT 16
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#define FIFO_STA_TXE 31
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/* SUNXI_SPDIF_INT register */
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#define INT_RXAIEN 0
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#define INT_RXOIEN 1
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#define INT_RXDRQEN 2
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#define INT_TXEIEN 4
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#define INT_TXOIEN 5
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#define INT_TXUIEN 6
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#define INT_TXDRQEN 7
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#define INT_RXPAREN 16
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#define INT_RXUNLOCKEN 17
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#define INT_RXLOCKEN 18
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/* SUNXI_SPDIF_INT_STA */
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#define INT_STA_RXA 0
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#define INT_STA_RXO 1
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#define INT_STA_TXE 4
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#define INT_STA_TXO 5
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#define INT_STA_TXU 6
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#define INT_STA_RXPAR 16
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#define INT_STA_RXUNLOCK 17
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#define INT_STA_RXLOCK 18
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/* SUNXI_SPDIF_TXCH_STA0 register */
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#define TXCHSTA0_PRO 0
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#define TXCHSTA0_AUDIO 1
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#define TXCHSTA0_CP 2
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#define TXCHSTA0_EMPHASIS 3
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#define TXCHSTA0_MODE 6
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#define TXCHSTA0_CATACOD 8
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#define TXCHSTA0_SRCNUM 16
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#define TXCHSTA0_CHNUM 20
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#define TXCHSTA0_SAMFREQ 24
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#define TXCHSTA0_CLK 28
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/* SUNXI_SPDIF_TXCH_STA1 register */
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#define TXCHSTA1_MAXWORDLEN 0
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#define TXCHSTA1_SAMWORDLEN 1
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#define TXCHSTA1_ORISAMFREQ 4
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#define TXCHSTA1_CGMSA 8
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/* SUNXI_SPDIF_RXCH_STA0 register */
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#define RXCHSTA0_PRO 0
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#define RXCHSTA0_AUDIO 1
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#define RXCHSTA0_CP 2
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#define RXCHSTA0_EMPHASIS 3
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#define RXCHSTA0_MODE 6
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#define RXCHSTA0_CATACOD 8
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#define RXCHSTA0_SRCNUM 16
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#define RXCHSTA0_CHNUM 20
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#define RXCHSTA0_SAMFREQ 24
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#define RXCHSTA0_CLK 28
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/* SUNXI_SPDIF_RXCH_STA1 register */
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#define RXCHSTA1_MAXWORDLEN 0
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#define RXCHSTA1_SAMWORDLEN 1
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#define RXCHSTA1_ORISAMFREQ 4
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#define RXCHSTA1_CGMSA 8
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struct sunxi_spdif_reg_label {
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const char *name;
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int value;
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};
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#if IS_ENABLED(CONFIG_SND_SUNXI_SOC_SUN50IW11_SPDIF_RX_IEC61937)
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/* SUNXI_SPDIF_EXP_CTL register */
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#define INSET_DET_NUM 0
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#define INSET_DET_EN 8
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#define SYNCW_BIT_EN 9
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#define DATA_TYPE_BIT_EN 10
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#define DATA_LEG_BIT_EN 11
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#define AUDIO_DATA_BIT_EN 12
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#define RX_MODE 13
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#define RX_MODE_MAN 14
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#define UNIT_SEL 15
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#define RPOTBF_NUM 16
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#define BURST_DATA_OUT_SEL 30
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/* SUNXI_SPDIF_EXP_ISTA register */
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#define INSET_INT 0
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#define PAPB_CAP_INT 1
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#define PCPD_CAP_INT 2
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#define RPDB_ERR_INT 3
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#define PC_DTYOE_CH_INT 4
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#define PC_ERR_FLAG_INT 5
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#define PC_BIT_CH_INT 6
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#define PC_PAUSE_STOP_INT 7
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#define PD_CHAN_INT 8
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#define INSET_INT_EN 16
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#define PAPB_CAP_INT_EN 17
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#define PCPD_CAP_INT_EN 18
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#define RPDB_ERR_INT_EN 19
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#define PC_DTYOE_CH_INT_EN 20
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#define PC_ERR_FLAG_INT_EN 21
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#define PC_BIT_CH_INT_EN 22
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#define PC_PAUSE_STOP_INT_EN 23
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#define PD_CHAN_INT_EN 24
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/* SUNXI_SPDIF_EXP_INFO0 register */
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#define PD_DATA_INFO 0
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#define PC_DATA_INFO 16
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/* SUNXI_SPDIF_EXP_INFO1 register */
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#define SAMPLE_RATE_VAL 0
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#define RPOTBF_VAL 16
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/* SUNXI_SPDIF_EXP_DBG0 register */
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#define RE_DATA_COUNT_VAL 0
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#define DATA_CAP_STA_MACHE 16
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/* SUNXI_SPDIF_EXP_DBG1 register */
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#define SAMPLE_RATE_COUNT 0
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#define RPOTBF_COUNT 16
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/* SUNXI_SPDIF_EXP_VER register */
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#define MOD_VER 0
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#endif
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#define SPDIF_REG_LABEL(constant) \
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{ \
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#constant, constant \
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}
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#define SPDIF_REG_LABEL_END \
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{ \
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NULL, -1 \
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}
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#define SPDIF_RX_FIFO_SIZE 64
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#define SPDIF_TX_FIFO_SIZE 128
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#define SPDIF_CLK_PLL_DIV5_FREQ 0
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#define SPDIF_CLK_PLL_DIV2_FREQ 1
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#define SPDIF_CLK_PLL_X1_FREQ_DOUBLE 2
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#define SPDIF_CLK_PLL_X4_FREQ_DOUBLE 3
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struct spdif_gpio_ {
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u32 gpio;
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bool level;
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bool used;
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};
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struct sunxi_spdif_mem_info {
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void __iomem *membase;
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struct resource *memregion;
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struct regmap *regmap;
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};
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struct sunxi_spdif_clk_info {
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struct clk *clk_pll;
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struct clk *clk_pllx4;
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struct clk *clk_module;
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#if IS_ENABLED(CONFIG_SND_SUNXI_SOC_SUN50IW11_SPDIF_RX_IEC61937)
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struct clk *clk_periph0;
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struct clk *clk_module_rx;
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#endif
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unsigned int clk_parent;
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};
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struct sunxi_spdif_pinctl_info {
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struct pinctrl *pinctrl;
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struct pinctrl_state *pinstate;
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struct pinctrl_state *pinstate_sleep;
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};
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struct sunxi_spdif_dts_info {
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struct sunxi_spdif_mem_info mem_info;
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struct sunxi_spdif_clk_info clk_info;
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struct sunxi_spdif_pinctl_info pin_info;
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struct spdif_gpio_ gpio_cfg;
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/* value must be (2^n)Kbyte */
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size_t playback_cma;
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size_t capture_cma;
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};
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#if IS_ENABLED(CONFIG_SND_SUNXI_SOC_SUN50IW11_SPDIF_RX_IEC61937)
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struct sunxi_spdif_rx_params {
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u32 freq;
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u32 orig_freq;
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u32 refreq;
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u32 channels;
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u32 bits;
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};
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struct sunxi_spdif_rx_info {
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#if 0
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u32 spdif_inset_int;
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u32 spdif_rxlock_int;
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u32 spdif_rxunlock_int;
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u32 spdif_papb_int;
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u32 channel_status;
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#endif
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struct sunxi_spdif_rx_params rx_params;
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};
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#endif
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struct sunxi_spdif_info {
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struct device *dev;
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struct sunxi_spdif_dts_info dts_info;
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struct mutex mutex;
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struct snd_soc_dai_driver dai;
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#if IS_ENABLED(CONFIG_SND_SUNXI_SOC_SUN50IW11_SPDIF_RX_IEC61937)
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struct sunxi_spdif_rx_info rx_info;
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unsigned int spdif_rx_type;
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/* spdif in irq */
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// int spdif_irq;
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#endif
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struct sunxi_dma_params playback_dma_param;
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struct sunxi_dma_params capture_dma_param;
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unsigned int rate;
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unsigned int active;
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bool configured;
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};
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#endif /* __SUNXI_SPDIF_H_ */
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