369 lines
9.6 KiB
C
369 lines
9.6 KiB
C
/*
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* sound\soc\sunxi\sun8iw19-daudio.h
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* (C) Copyright 2014-2019
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* yumingfeng <yumingfeng@allwinertech.com>
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*
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* some simple description for this code
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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*/
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#ifndef __SUN8IW19_DAUDIO_H_
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#define __SUN8IW19_DAUDIO_H_
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#include "sun8iw19-pcm.h"
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#include "sun8iw19-codec.h"
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/*
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* Platform I2S_count HDMI_seq(index is 0 to i) MODE
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* sun8iw19 2 NONE B(TDM:16-channels)
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*/
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/* DAUDIO register definition */
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#define SUNXI_DAUDIO_CTL 0x00
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#define SUNXI_DAUDIO_FMT0 0x04
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#define SUNXI_DAUDIO_FMT1 0x08
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#define SUNXI_DAUDIO_INTSTA 0x0C
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#define SUNXI_DAUDIO_RXFIFO 0x10
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#define SUNXI_DAUDIO_FIFOCTL 0x14
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#define SUNXI_DAUDIO_FIFOSTA 0x18
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#define SUNXI_DAUDIO_INTCTL 0x1C
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#define SUNXI_DAUDIO_TXFIFO 0x20
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#define SUNXI_DAUDIO_CLKDIV 0x24
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#define SUNXI_DAUDIO_TXCNT 0x28
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#define SUNXI_DAUDIO_RXCNT 0x2C
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#define SUNXI_DAUDIO_CHCFG 0x30
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#define SUNXI_DAUDIO_TX0CHSEL 0x34
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#define SUNXI_DAUDIO_TX1CHSEL 0x38
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#define SUNXI_DAUDIO_TX2CHSEL 0x3C
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#define SUNXI_DAUDIO_TX3CHSEL 0x40
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#define SUNXI_DAUDIO_TX0CHMAP0 0x44
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#define SUNXI_DAUDIO_TX0CHMAP1 0x48
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#define SUNXI_DAUDIO_TX1CHMAP0 0x4C
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#define SUNXI_DAUDIO_TX1CHMAP1 0x50
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#define SUNXI_DAUDIO_TX2CHMAP0 0x54
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#define SUNXI_DAUDIO_TX2CHMAP1 0x58
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#define SUNXI_DAUDIO_TX3CHMAP0 0x5C
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#define SUNXI_DAUDIO_TX3CHMAP1 0x60
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#define SUNXI_DAUDIO_RXCHSEL 0x64
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#define SUNXI_DAUDIO_RXCHMAP0 0x68
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#define SUNXI_DAUDIO_RXCHMAP1 0x6C
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#define SUNXI_DAUDIO_RXCHMAP2 0x70
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#define SUNXI_DAUDIO_RXCHMAP3 0x74
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#define SUNXI_DAUDIO_DEBUG 0x78
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#define SUNXI_DAUDIO_REV 0x7C
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#define SUNXI_DAUDIO_REG_NUM_MAX (SUNXI_DAUDIO_DEBUG >> 2)
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/* SUNXI_DAUDIO_CTL:0x00 */
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#define RX_SYNC_EN 21
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#define RX_EN_MUX 20
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#define BCLK_OUT 18
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#define LRCK_OUT 17
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#define LRCKR_CTL 16
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#define SDO3_EN 11
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#define SDO2_EN 10
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#define SDO1_EN 9
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#define SDO0_EN 8
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#define MUTE_CTL 6
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#define MODE_SEL 4
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#define LOOP_EN 3
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#define CTL_TXEN 2
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#define CTL_RXEN 1
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#define GLOBAL_EN 0
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/* SUNXI_DAUDIO_FMT0:0x04 */
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#define SDI_SYNC_SEL 31
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#define LRCK_WIDTH 30
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#define LRCKR_PERIOD 20
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#define LRCK_POLARITY 19
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#define LRCK_PERIOD 8
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#define BRCK_POLARITY 7
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#define DAUDIO_SAMPLE_RESOLUTION 4
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#define EDGE_TRANSFER 3
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#define SLOT_WIDTH 0
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/* SUNXI_DAUDIO_FMT1:0x08 */
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#define RX_MLS 7
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#define TX_MLS 6
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#define SEXT 4
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#define RX_PDM 2
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#define TX_PDM 0
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/* SUNXI_DAUDIO_INTSTA:0x0C */
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#define TXU_INT 6
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#define TXO_INT 5
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#define TXE_INT 4
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#define RXU_INT 2
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#define RXO_INT 1
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#define RXA_INT 0
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/* SUNXI_DAUDIO_FIFOCTL:0x14 */
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#define HUB_EN 31
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#define FIFO_CTL_FTX 25
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#define FIFO_CTL_FRX 24
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#define TXTL 12
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#define RXTL 4
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#define TXIM 2
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#define RXOM 0
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/* SUNXI_DAUDIO_FIFOSTA:0x18 */
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#define FIFO_TXE 28
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#define FIFO_TX_CNT 16
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#define FIFO_RXA 8
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#define FIFO_RX_CNT 0
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/* SUNXI_DAUDIO_INTCTL:0x1C */
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#define TXDRQEN 7
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#define TXUI_EN 6
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#define TXOI_EN 5
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#define TXEI_EN 4
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#define RXDRQEN 3
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#define RXUIEN 2
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#define RXOIEN 1
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#define RXAIEN 0
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/* SUNXI_DAUDIO_CLKDIV:0x24 */
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#define MCLKOUT_EN 8
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#define BCLK_DIV 4
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#define MCLK_DIV 0
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/* SUNXI_DAUDIO_CHCFG:0x30 */
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#define TX_SLOT_HIZ 9
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#define TX_STATE 8
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#define RX_SLOT_NUM 4
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#define TX_SLOT_NUM 0
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/* SUNXI_DAUDIO_TXnCHSEL:0X34+n*0x04 */
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#define TX_OFFSET 20
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#define TX_CHSEL 16
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#define TX_CHEN 0
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/* SUNXI_DAUDIO_RXCHSEL */
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#define RX_OFFSET 20
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#define RX_CHSEL 16
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/* sun8iw19 CHMAP default setting */
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#define SUNXI_DEFAULT_CHMAP0 0xFEDCBA98
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#define SUNXI_DEFAULT_CHMAP1 0x76543210
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/* RXCHMAP default setting */
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#define SUNXI_DEFAULT_CHMAP 0x76543210
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/* Shift & Mask define */
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/* SUNXI_DAUDIO_CTL:0x00 */
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#define SUNXI_DAUDIO_MODE_CTL_MASK 3
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#define SUNXI_DAUDIO_MODE_CTL_PCM 0
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#define SUNXI_DAUDIO_MODE_CTL_I2S 1
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#define SUNXI_DAUDIO_MODE_CTL_LEFT 1
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#define SUNXI_DAUDIO_MODE_CTL_RIGHT 2
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#define SUNXI_DAUDIO_MODE_CTL_REVD 3
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/* combine LRCK_CLK & BCLK setting */
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#define SUNXI_DAUDIO_LRCK_OUT_MASK 3
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#define SUNXI_DAUDIO_LRCK_OUT_DISABLE 0
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#define SUNXI_DAUDIO_LRCK_OUT_ENABLE 3
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/* SUNXI_DAUDIO_FMT0 */
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#define SUNXI_DAUDIO_LRCK_PERIOD_MASK 0x3FF
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#define SUNXI_DAUDIO_SLOT_WIDTH_MASK 7
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/* Left Blank */
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#define SUNXI_DAUDIO_SR_MASK 7
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#define SUNXI_DAUDIO_SR_16BIT 3
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#define SUNXI_DAUDIO_SR_24BIT 5
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#define SUNXI_DAUDIO_SR_32BIT 7
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#define SUNXI_DAUDIO_LRCK_POLARITY_NOR 0
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#define SUNXI_DAUDIO_LRCK_POLARITY_INV 1
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#define SUNXI_DAUDIO_BCLK_POLARITY_NOR 0
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#define SUNXI_DAUDIO_BCLK_POLARITY_INV 1
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/* SUNXI_DAUDIO_FMT1 */
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#define SUNXI_DAUDIO_FMT1_DEF 0x30
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/* SUNXI_DAUDIO_FIFOCTL */
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#define SUNXI_DAUDIO_TXIM_MASK 1
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#define SUNXI_DAUDIO_TXIM_VALID_MSB 0
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#define SUNXI_DAUDIO_TXIM_VALID_LSB 1
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/* Left Blank */
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#define SUNXI_DAUDIO_RXOM_MASK 3
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/* Expanding 0 at LSB of RX_FIFO */
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#define SUNXI_DAUDIO_RXOM_EXP0 0
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/* Expanding sample bit at MSB of RX_FIFO */
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#define SUNXI_DAUDIO_RXOM_EXPH 1
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/* Fill RX_FIFO low word be 0 */
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#define SUNXI_DAUDIO_RXOM_TUNL 2
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/* Fill RX_FIFO high word be higher sample bit */
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#define SUNXI_DAUDIO_RXOM_TUNH 3
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/* SUNXI_DAUDIO_CLKDIV */
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#define SUNXI_DAUDIO_BCLK_DIV_MASK 0xF
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#define SUNXI_DAUDIO_BCLK_DIV_1 1
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#define SUNXI_DAUDIO_BCLK_DIV_2 2
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#define SUNXI_DAUDIO_BCLK_DIV_3 3
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#define SUNXI_DAUDIO_BCLK_DIV_4 4
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#define SUNXI_DAUDIO_BCLK_DIV_5 5
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#define SUNXI_DAUDIO_BCLK_DIV_6 6
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#define SUNXI_DAUDIO_BCLK_DIV_7 7
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#define SUNXI_DAUDIO_BCLK_DIV_8 8
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#define SUNXI_DAUDIO_BCLK_DIV_9 9
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#define SUNXI_DAUDIO_BCLK_DIV_10 10
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#define SUNXI_DAUDIO_BCLK_DIV_11 11
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#define SUNXI_DAUDIO_BCLK_DIV_12 12
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#define SUNXI_DAUDIO_BCLK_DIV_13 13
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#define SUNXI_DAUDIO_BCLK_DIV_14 14
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#define SUNXI_DAUDIO_BCLK_DIV_15 15
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/* Left Blank */
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#define SUNXI_DAUDIO_MCLK_DIV_MASK 0xF
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#define SUNXI_DAUDIO_MCLK_DIV_1 1
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#define SUNXI_DAUDIO_MCLK_DIV_2 2
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#define SUNXI_DAUDIO_MCLK_DIV_3 3
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#define SUNXI_DAUDIO_MCLK_DIV_4 4
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#define SUNXI_DAUDIO_MCLK_DIV_5 5
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#define SUNXI_DAUDIO_MCLK_DIV_6 6
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#define SUNXI_DAUDIO_MCLK_DIV_7 7
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#define SUNXI_DAUDIO_MCLK_DIV_8 8
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#define SUNXI_DAUDIO_MCLK_DIV_9 9
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#define SUNXI_DAUDIO_MCLK_DIV_10 10
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#define SUNXI_DAUDIO_MCLK_DIV_11 11
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#define SUNXI_DAUDIO_MCLK_DIV_12 12
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#define SUNXI_DAUDIO_MCLK_DIV_13 13
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#define SUNXI_DAUDIO_MCLK_DIV_14 14
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#define SUNXI_DAUDIO_MCLK_DIV_15 15
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/* SUNXI_DAUDIO_CHCFG */
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#ifdef SUNXI_DAUDIO_MODE_B
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#define SUNXI_DAUDIO_TX_SLOT_MASK 0XF
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#define SUNXI_DAUDIO_RX_SLOT_MASK 0XF
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#else
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#define SUNXI_DAUDIO_TX_SLOT_MASK 7
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#define SUNXI_DAUDIO_RX_SLOT_MASK 7
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#endif
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/* SUNXI_DAUDIO_TX0CHSEL: */
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#define SUNXI_DAUDIO_TX_OFFSET_MASK 3
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#define SUNXI_DAUDIO_TX_OFFSET_0 0
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#define SUNXI_DAUDIO_TX_OFFSET_1 1
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/* Left Blank */
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#define SUNXI_DAUDIO_TX_CHEN_MASK 0xFFFF
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#define SUNXI_DAUDIO_TX_CHSEL_MASK 0xF
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/* SUNXI_DAUDIO_RXCHSEL */
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#define SUNXI_DAUDIO_RX_OFFSET_MASK 3
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#define SUNXI_DAUDIO_RX_CHSEL_MASK 0XF
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#define DAUDIO_RXCH_DEF_MAP(x) (x << ((x%4)<<3))
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#define DAUDIO_RXCHMAP(x) (0x1f << ((x%4)<<3))
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/*
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* For other define.
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*/
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#define SND_SOC_DAIFMT_SIG_SHIFT 8
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#define SND_SOC_DAIFMT_MASTER_SHIFT 12
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#define USE_ASOC_FMT_SETTING
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/*
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* some platform just not support four channel daudio,
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* so make the 3rd channel define as NULL for codec compile
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*/
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/* sun8iw19p1 just use i2s0/i2s1 */
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#define DRQDST_HDMI_TX 0
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#define DRQDST_DAUDIO_2_TX 0
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#define DRQSRC_DAUDIO_2_RX 0
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#define DRQSRC_DAUDIO_3_RX 0
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#define DRQDST_DAUDIO_3_TX 0
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#define DAUDIO_NUM_MAX 2
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#ifndef DAUDIO_NUM_MAX
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#define DAUDIO_NUM_MAX 4
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#endif
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#define SUNXI_DAUDIO_BCLK 0
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#define SUNXI_DAUDIO_LRCK 1
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#define SUNXI_DAUDIO_MCLK 2
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#define SUNXI_DAUDIO_GEN 3
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/*to clear FIFO*/
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#define SUNXI_DAUDIO_FTX_TIMES 3
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struct daudio_reg_label {
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const char *name;
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const unsigned long address;
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int value;
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};
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#define REG_LABEL(constant) {#constant, constant, 0}
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#define REG_LABEL_END {NULL, -1, 0}
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struct sunxi_daudio_platform_data {
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unsigned int daudio_type;
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unsigned int external_type;
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/* should be setup at machine driver. */
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unsigned int daudio_master;
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unsigned int audio_format;
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unsigned int signal_inversion;
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unsigned int pcm_lrck_period;
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unsigned int msb_lsb_first:1;
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unsigned int sign_extend:2;
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unsigned int tx_data_mode:2;
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unsigned int rx_data_mode:2;
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unsigned int slot_width_select;
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unsigned int frame_type;
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unsigned int tdm_config;
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unsigned int tdm_num;
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unsigned int mclk_div;
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};
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struct daudio_label {
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unsigned int address;
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int value;
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};
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struct voltage_supply {
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struct regulator *daudio_regulator;
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const char *regulator_name;
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};
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struct sunxi_daudio_info {
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struct device *dev;
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struct resource res;
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struct regmap *regmap;
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void __iomem *membase;
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struct resource *memregion;
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struct clk *pllclk;
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struct clk *moduleclk;
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struct voltage_supply vol_supply;
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struct mutex mutex;
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struct mutex global_mutex;
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struct sunxi_dma_params playback_dma_param;
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struct sunxi_dma_params capture_dma_param;
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struct pinctrl *pinctrl;
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struct pinctrl_state *pinstate;
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struct pinctrl_state *pinstate_sleep;
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struct sunxi_daudio_platform_data *pdata;
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unsigned int hub_mode;
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bool playback_en;
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bool capture_en;
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int global_enable;
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struct snd_soc_dai *cpu_dai;
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struct daudio_label *reg_label;
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};
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void sunxi_daudio_rxctrl_enable(struct sunxi_daudio_info *sunxi_daudio,
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bool enable);
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int sunxi_daudio_global_enable(struct sunxi_daudio_info *sunxi_daudio,
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bool enable);
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#ifdef CONFIG_SUNXI_ADC_DAUDIO_SYNC
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void sunxi_daudio_rx_drq_enable(void *sunxi_daudio, bool enable);
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#endif
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#endif /* __SUN8IW19_DAUDIO_H_ */
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