179 lines
4.1 KiB
C
179 lines
4.1 KiB
C
/* sound\soc\sunxi\snd_sunxi_dmic.h
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* (C) Copyright 2021-2025
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Dby <dby@allwinnertech.com>
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*
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* some simple description for this code
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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*/
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#ifndef __SND_SUNXI_DMIC_H
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#define __SND_SUNXI_DMIC_H
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#define SUNXI_DMIC_EN 0x00
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#define SUNXI_DMIC_SR 0x04
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#define SUNXI_DMIC_CTR 0x08
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#define SUNXI_DMIC_DATA 0x10
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#define SUNXI_DMIC_INTC 0x14
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#define SUNXI_DMIC_INTS 0x18
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#define SUNXI_DMIC_FIFO_CTR 0x1c
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#define SUNXI_DMIC_FIFO_STA 0x20
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#define SUNXI_DMIC_CH_NUM 0x24
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#define SUNXI_DMIC_CH_MAP 0x28
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#define SUNXI_DMIC_CNT 0x2c
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#define SUNXI_DMIC_DATA0_1_VOL 0x30
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#define SUNXI_DMIC_DATA2_3_VOL 0x34
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#define SUNXI_DMIC_HPF_CTRL 0x38
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#define SUNXI_DMIC_HPF_COEF 0x3C
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#define SUNXI_DMIC_HPF_GAIN 0x40
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#define SUNXI_DMIC_REV 0x50
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#define SUNXI_DMIC_REG_MAX SUNXI_DMIC_REV
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/*0x00:SUNXI_DMIC_EN*/
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#define RX_SYNC_EN_START 29
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#define RX_SYNC_EN 28
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#define GLOBE_EN 8
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#define DATA3_CHR_EN 7
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#define DATA3_CHL_EN 6
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#define DATA2_CHR_EN 5
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#define DATA2_CHL_EN 4
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#define DATA1_CHR_EN 3
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#define DATA1_CHL_EN 2
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#define DATA0_CHR_EN 1
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#define DATA0_CHL_EN 0
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#define DATA_CH_EN 0
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/*SUNXI_DMIC_SR:0x04*/
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#define DMIC_SR 0
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/*SUNXI_DMIC_CTR:0x08*/
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#define DMICFDT 9
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#define DMICDFEN 8
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#define DATA3_LR_SWAP_EN 7
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#define DATA2_LR_SWAP_EN 6
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#define DATA1_LR_SWAP_EN 5
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#define DATA0_LR_SWAP_EN 4
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#define DMIC_OVERSAMPLE_RATE 0
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/*SUNXI_DMIC_DATA:0x10*/
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#define DMIC_DATA 0
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/*SUNXI_DMIC_INTC:0x14*/
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#define FIFO_DRQ_EN 2
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#define FIFO_OVERRUN_IRQ_EN 1
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#define DATA_IRQ_EN 0
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/*SUNXI_DMIC_INTS:0x18*/
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#define FIFO_OVERRUN_IRQ_PENDING 1
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#define FIFO_DATA_IRQ_PENDING 0
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/*SUNXI_DMIC_FIFO_CTR:0x1c*/
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#define DMIC_FIFO_FLUSH 31
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#define DMIC_FIFO_MODE 9
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#define DMIC_SAMPLE_RESOLUTION 8
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#define FIFO_TRG_LEVEL 0
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/*SUNXI_DMIC_FIFO_STA:0x20*/
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#define DMIC_DATA_CNT 0
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/*SUNXI_DMIC_CH_NUM:0x24*/
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#define DMIC_CH_NUM 0
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/*SUNXI_DMIC_CH_MAP:0x28*/
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#define DMIC_CH7_MAP 28
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#define DMIC_CH6_MAP 24
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#define DMIC_CH5_MAP 20
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#define DMIC_CH4_MAP 16
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#define DMIC_CH3_MAP 12
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#define DMIC_CH2_MAP 8
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#define DMIC_CH1_MAP 4
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#define DMIC_CH0_MAP 0
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#define DMIC_CHANMAP_DEFAULT (0x76543210)
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/*SUNXI_DMIC_CNT:0x2c*/
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#define DMIC_CNT 0
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/*SUNXI_DMIC_DATA0_1_VOL:0x30*/
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#define DATA1L_VOL 24
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#define DATA1R_VOL 16
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#define DATA0L_VOL 8
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#define DATA0R_VOL 0
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/*SUNXI_DMIC_DATA2_3_VOL:0x34*/
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#define DATA3L_VOL 24
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#define DATA3R_VOL 16
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#define DATA2L_VOL 8
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#define DATA2R_VOL 0
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#define DMIC_DEFAULT_VOL 0xB0
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/*SUNXI_DMIC_HPF_EN_CTR:0x38*/
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#define HPF_DATA3_CHR_EN 7
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#define HPF_DATA3_CHL_EN 6
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#define HPF_DATA2_CHR_EN 5
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#define HPF_DATA2_CHL_EN 4
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#define HPF_DATA1_CHR_EN 3
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#define HPF_DATA1_CHL_EN 2
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#define HPF_DATA0_CHR_EN 1
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#define HPF_DATA0_CHL_EN 0
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/*SUNXI_DMIC_HPF_COEF:0x3C*/
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#define HPF_COEF 0
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/*SUNXI_DMIC_HPF_GAIN:0x40*/
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#define HPF_GAIN 0
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#ifdef CONFIG_ARCH_SUN8IW21
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#include "platforms/snd_sun8iw21_dmic.h"
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/* e.g.
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* #elif defined(CONFIG_ARCH_SUNXXIWXX)
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* #include "platforms/snd_sunxxiwxx_dmic.h"
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*/
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#endif
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struct sunxi_dmic_mem {
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struct resource res;
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void __iomem *membase;
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struct resource *memregion;
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struct regmap *regmap;
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};
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struct sunxi_dmic_pinctl {
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struct pinctrl *pinctrl;
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struct pinctrl_state *pinstate;
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struct pinctrl_state *pinstate_sleep;
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bool pinctrl_used;
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};
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struct sunxi_dmic_dts {
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/* value must be (2^n)Kbyte */
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size_t capture_cma;
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size_t capture_fifo_size;
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unsigned int rx_chmap;
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unsigned int data_vol;
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unsigned int rx_dtime;
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/* components func -> rx_sync */
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bool rx_sync_en; /* read from dts */
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bool rx_sync_ctl;
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int rx_sync_id;
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rx_sync_domain_t rx_sync_domain;
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};
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struct sunxi_dmic {
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struct platform_device *pdev;
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struct sunxi_dmic_mem mem;
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struct sunxi_dmic_clk clk;
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struct sunxi_dmic_pinctl pin;
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struct sunxi_dmic_dts dts;
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struct sunxi_dma_params capture_dma_param;
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};
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#endif /* __SND_SUNXI_DMIC_H */
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