172 lines
9.6 KiB
C
Executable File
172 lines
9.6 KiB
C
Executable File
/* Copyright (c) 2019-2025 Allwinner Technology Co., Ltd. ALL rights reserved.
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*
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* Allwinner is a trademark of Allwinner Technology Co.,Ltd., registered in
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*the the People's Republic of China and other countries.
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* All Allwinner Technology Co.,Ltd. trademarks are used with permission.
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*
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* DISCLAIMER
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* THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT.
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* IF YOU NEED TO INTEGRATE THIRD PARTY’S TECHNOLOGY (SONY, DTS, DOLBY, AVS OR MPEGLA, ETC.)
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* IN ALLWINNERS’SDK OR PRODUCTS, YOU SHALL BE SOLELY RESPONSIBLE TO OBTAIN
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* ALL APPROPRIATELY REQUIRED THIRD PARTY LICENCES.
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* ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS
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* COVERED UNDER ANY REQUIRED THIRD PARTY LICENSE.
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* YOU ARE SOLELY RESPONSIBLE FOR YOUR USAGE OF THIRD PARTY’S TECHNOLOGY.
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*
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*
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* THIS SOFTWARE IS PROVIDED BY ALLWINNER"AS IS" AND TO THE MAXIMUM EXTENT
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* PERMITTED BY LAW, ALLWINNER EXPRESSLY DISCLAIMS ALL WARRANTIES OF ANY KIND,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION REGARDING
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* THE TITLE, NON-INFRINGEMENT, ACCURACY, CONDITION, COMPLETENESS, PERFORMANCE
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* OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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* IN NO EVENT SHALL ALLWINNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS, OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __SUN8IW21P1_CLK_H__
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#define __SUN8IW21P1_CLK_H__
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#include <stdio.h>
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#include <string.h>
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#include <hal_clk.h>
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#include "../clk.h"
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#define CLK_PARENT_MAX 6
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// clk_fixed_factor_pt sunxi_clk_fixed_factor_arry[SUNXI_CLK_FIXED_FACTOR_MAX];
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#define SUNXI_CLK_FACTOR_CPU_MAX_FREQ (1296000000U)
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#define SUNXI_CLK_FACTOR_DDR0_MAX_FREQ (2520000000U)
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#define SUNXI_CLK_FACTOR_PERIPH0X2_MAX_FREQ (1200000000U)
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#define SUNXI_CLK_FACTOR_PERIPH0800M_MAX_FREQ (1200000000U)
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#define SUNXI_CLK_FACTOR_PERIPH0480M_MAX_FREQ (1200000000U)
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#define SUNXI_CLK_FACTOR_VIDEO0X4_MAX_FREQ (1188000000U)
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#define SUNXI_CLK_FACTOR_CSIX4_MAX_FREQ (2376000000U)
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#define SUNXI_CLK_FACTOR_AUDIO_MAX_FREQ (288000000U)
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#define SUNXI_CLK_FACTOR_NPUX4_MAX_FREQ (1188000000U)
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/********************************************************************************/
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/* CCMU Register List */
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#define CCU_REG_BASE (0x02001000)
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#define CLK_PLL_CPU (volatile uint32_t *)(CCU_REG_BASE + 0x0000)
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#define CLK_PLL_DDR (volatile uint32_t *)(CCU_REG_BASE + 0x0010)
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#define CLK_PLL_PERIPH0 (volatile uint32_t *)(CCU_REG_BASE + 0x0020)
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#define CLK_PLL_VIDEO0 (volatile uint32_t *)(CCU_REG_BASE + 0x0040)
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#define CLK_PLL_CSI (volatile uint32_t *)(CCU_REG_BASE + 0x0048)
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#define CLK_PLL_AUDIO (volatile uint32_t *)(CCU_REG_BASE + 0x0078)
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#define CLK_PLL_NPU (volatile uint32_t *)(CCU_REG_BASE + 0x0080)
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#define CLK_PLL_DDRPAT (volatile uint32_t *)(CCU_REG_BASE + 0x0110)
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#define CLK_PLL_PERI0PAT0 (volatile uint32_t *)(CCU_REG_BASE + 0x0120)
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#define CLK_PLL_PERI0PAT1 (volatile uint32_t *)(CCU_REG_BASE + 0x0124)
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#define CLK_PLL_VIDEO0PAT0 (volatile uint32_t *)(CCU_REG_BASE + 0x0140)
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#define CLK_PLL_VIDEO0PAT1 (volatile uint32_t *)(CCU_REG_BASE + 0x0144)
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#define CLK_PLL_CSIPAT0 (volatile uint32_t *)(CCU_REG_BASE + 0x0148)
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#define CLK_PLL_CSIPAT1 (volatile uint32_t *)(CCU_REG_BASE + 0x014C)
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#define CLK_PLL_AUDIOPAT0 (volatile uint32_t *)(CCU_REG_BASE + 0x0178)
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#define CLK_PLL_AUDIOPAT1 (volatile uint32_t *)(CCU_REG_BASE + 0x017C)
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#define CLK_PLL_NPUPAT0 (volatile uint32_t *)(CCU_REG_BASE + 0x0180)
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#define CLK_PLL_NPUPAT1 (volatile uint32_t *)(CCU_REG_BASE + 0x0184)
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#define CLK_CPU_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0500)
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#define CLK_AHB_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0510)
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#define CLK_APB0_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0520)
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#define CLK_APB1_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0524)
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#define CLK_MBUS_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0540)
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/* Accelerator */
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#define CLK_DE_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0600)
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#define CLK_DE_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x060C)
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#define CLK_G2D_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0630)
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#define CLK_G2D_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x063C)
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#define CLK_CE_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0680)
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#define CLK_CE_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x068C)
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#define CLK_VE_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0690)
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#define CLK_VE_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x069C)
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#define CLK_NPU_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x06E0)
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#define CLK_NPU_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x06EC)
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/* SYS Resource */
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#define CLK_DMA_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x070C)
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#define CLK_MSGBOX_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x071C)
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#define CLK_SPINLOCK_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x072C)
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#define CLK_HSTIMER_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x073C)
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#define CLK_AVS_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0740)
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#define CLK_DBGSYS_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x078C)
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#define CLK_PSI_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x079C)
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#define CLK_PWM_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x07AC)
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#define CLK_IOMMU_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x07BC)
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/* Storage Medium */
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#define CLK_DRAM_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0800)
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#define CLK_MBUS_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x0804)
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#define CLK_DRAM_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x080C)
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#define CLK_SMHC0_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0830)
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#define CLK_SMHC1_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0834)
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#define CLK_SMHC2_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0838)
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#define CLK_SMHC_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x084C)
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/* Common Interface */
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#define CLK_UART_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x090C)
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#define CLK_TWI_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x091C)
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#define CLK_SPI0_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0940)
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#define CLK_SPI1_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0944)
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#define CLK_SPI2_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0948)
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#define CLK_SPI3_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x094C)
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#define CLK_SPIF_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0950)
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#define CLK_SPI_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x096C)
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#define CLK_GMAC25M_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0970)
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#define CLK_GMAC_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x097C)
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#define CLK_GPADC_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x09EC)
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#define CLK_THS_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x09FC)
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#define CLK_I2S0_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0A10)
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#define CLK_I2S1_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0A14)
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#define CLK_I2S_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x0A20)
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#define CLK_DMIC_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0A40)
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#define CLK_DMIC_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x0A4C)
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#define CLK_CODEC_DAC_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0A50)
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#define CLK_CODEC_ADC_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0A54)
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#define CLK_CODEC_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x0A5C)
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#define CLK_USB0_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0A70)
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#define CLK_USB_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x0A8C)
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/* Display Interface */
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#define CLK_DPSS_TOP_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x0ABC)
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#define CLK_DSI_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0B24)
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#define CLK_DSI_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x0B4C)
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#define CLK_TCON_LCD_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0B60)
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#define CLK_TCON_LCD_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x0B7C)
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#define CLK_CSI_TOP_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0C04)
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#define CLK_CSI_MASTER0_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0C08)
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#define CLK_CSI_MASTER1_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0C0C)
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#define CLK_CSI_MASTER2_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0C10)
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#define CLK_ISP_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0C20)
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#define CLK_CSI_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x0C2C)
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#define CLK_DSPO_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0C60)
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#define CLK_DSPO_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x0C6C)
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#define CLK_WIEGAND_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x0C7C)
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#define CLK_E907_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0D00)
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#define CLK_RISCV_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x0D0C)
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#define CLK_PLL_PRE_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0E00)
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#define CLK_GPADC_SEL (volatile uint32_t *)(CCU_REG_BASE + 0x0F04)
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#define CLK_FANOUT_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x0F30)
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#define CLK_FANOUT27M_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0F34)
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#define CLK_FANOUTPCLK_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0F38)
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#define CLK_CCMU_FANOUT_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0F3C)
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#endif /* __SUN8IW21P1_CLK_H__ */
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