131 lines
3.7 KiB
C
131 lines
3.7 KiB
C
/*
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* dspo_param.h
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*
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* Copyright (c) 2007-2021 Allwinnertech Co., Ltd.
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* Author: zhengxiaobin <zhengxiaobin@allwinnertech.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef _DSPO_PARAM_H
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#define _DSPO_PARAM_H
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#include "linux/kernel.h"
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#include "linux/mm.h"
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#include <asm/uaccess.h>
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#include <asm/memory.h>
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#include <asm/unistd.h>
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#include "linux/semaphore.h"
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#include <linux/vmalloc.h>
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#include <linux/types.h>
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#include <linux/fb.h>
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#include <linux/sched.h>
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#include <linux/err.h>
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#include <linux/delay.h>
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#include "asm-generic/int-ll64.h"
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#include <linux/module.h>
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#include <linux/errno.h>
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#include <linux/string.h>
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//interrupt define
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#define DSPO_V_INT 0x1
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#define DSPO_L_INT 0x2
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#define DSPO_DMA_DONE_INT 0x4
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#define DSPO_DMA_DESC_INT 0x8
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#define DSPO_FRAME_DONE_INT 0x10
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#define DSPO_LINE_DONE_INT 0x20
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#define DSPO_UV_LINE_DONE_INT 0x40
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#define DSPO_UV_BUF_UF_INT 0x80
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#define DSPO_UV_BUF_OF_INT 0x100
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#define DSPO_Y_BUF_UF_INT 0x200
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#define DSPO_Y_BUF_OF_INT 0x400
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//program define
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//dma or aidb select define
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#define DMA_DATA_PATH 0
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#define AIDB_DATA_PATH 1
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//data seq define
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// bt656 bt1120
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#define CbYCrY 0x0 //pass pass
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#define CrYCbY 0x1 //pass pass
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#define YCbYCr 0x2 //pass pass
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#define YCrYCb 0x3 //pass pass
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//embedded sync fmt define
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#define Embedded_SYNC_BT1120 0 //pass
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#define Embedded_SYNC_BT656 1 //pass
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//data src define
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#define YUV444_TO_PG 0 //pass
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#define YUV422_TO_PG 1 //pass
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//progress or interlace define
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#define PROGRESS 0 //pass
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#define INTERLACE 1
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//output data width define
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#define DATA_8Bit 0 //pass
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#define DATA_16Bit 1 //pass
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//interlace mode option define
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#define INTER_BT1120 0 //pass
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#define INTER_BT656 1 //pass
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//sync signal polarity
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// bt1120 bt656
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#define HIGH_ACTIVE 0 //pass pass
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#define LOW_ACTIVE 1 //pass pass
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//clk invert bt1120 pass;bt656 pass
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//dma descriptor mode define
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#define DRAM_GET_MODE 0
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#define REG_SET_MODE 1 //pass
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//dspo work mode define
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#define Normal_Mode 0 //pass
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#define Tri_Mode 1 //pass
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//dma block size select define
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#define BYTES_256 0x0
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#define BYTES_512 0x1
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#define BYTES_1024 0x2
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#define BYTES_2048 0x3
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//dma input data type define
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// bt656 bt1120
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#define ARGB888 0x0 //pass pass
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#define YUV444 0x1 //pass pass
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#define YUV422_YUYV 0x4 //pass pass
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#define YUV422_UYVY 0x5 //pass pass
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#define YUV422_YVYU 0x6 //pass pass
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#define YUV422_VYUY 0x7 //pass pass
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#define YUV422_Y_UVUV 0x8 //pass pass
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#define YUV422_Y_VUVU 0xa //pass pass
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#define YUV420_Y_UVUV 0xc //pass pass
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#define YUV420_Y_VUVU 0xe //pass pass
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struct csi_dma_des {
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u32 config;
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u32 pkt_type;
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u32 source_format;
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u32 buff0_addr;
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u32 buff1_addr;
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u32 buff0_line_stride;
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u32 buff1_line_stride;
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u32 next_des_addr;
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// struct csi_dma_des *virt_next; /*Next CPU virtual structure address*/
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};
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#endif /* DSPO_PARAM_H_ */
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