197 lines
5.8 KiB
C
197 lines
5.8 KiB
C
/*
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* Copyright (c) 2019-2025 Allwinner Technology Co., Ltd. ALL rights reserved.
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*
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* Allwinner is a trademark of Allwinner Technology Co.,Ltd., registered in
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* the the People's Republic of China and other countries.
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* All Allwinner Technology Co.,Ltd. trademarks are used with permission.
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*
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* DISCLAIMER
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* THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT.
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* IF YOU NEED TO INTEGRATE THIRD PARTY’S TECHNOLOGY (SONY, DTS, DOLBY, AVS OR MPEGLA, ETC.)
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* IN ALLWINNERS’SDK OR PRODUCTS, YOU SHALL BE SOLELY RESPONSIBLE TO OBTAIN
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* ALL APPROPRIATELY REQUIRED THIRD PARTY LICENCES.
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* ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS
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* COVERED UNDER ANY REQUIRED THIRD PARTY LICENSE.
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* YOU ARE SOLELY RESPONSIBLE FOR YOUR USAGE OF THIRD PARTY’S TECHNOLOGY.
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*
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*
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* THIS SOFTWARE IS PROVIDED BY ALLWINNER"AS IS" AND TO THE MAXIMUM EXTENT
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* PERMITTED BY LAW, ALLWINNER EXPRESSLY DISCLAIMS ALL WARRANTIES OF ANY KIND,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION REGARDING
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* THE TITLE, NON-INFRINGEMENT, ACCURACY, CONDITION, COMPLETENESS, PERFORMANCE
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* OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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* IN NO EVENT SHALL ALLWINNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS, OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <csr.h>
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#define L1_CACHE_BYTES (32)
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static void dcache_wb_range(unsigned long start, unsigned long end)
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{
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unsigned long i = start & ~(L1_CACHE_BYTES - 1);
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for (; i < end; i += L1_CACHE_BYTES)
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{
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asm volatile("dcache.cpa %0\n"::"r"(i):"memory");
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}
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asm volatile("fence.i":::"memory");
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}
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static void dcache_inv_range(unsigned long start, unsigned long end)
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{
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unsigned long i = start & ~(L1_CACHE_BYTES - 1);
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for (; i < end; i += L1_CACHE_BYTES)
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{
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asm volatile("dcache.ipa %0\n"::"r"(i):"memory");
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}
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asm volatile("fence.i":::"memory");
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}
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static void dcache_wbinv_range(unsigned long start, unsigned long end)
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{
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unsigned long i = start & ~(L1_CACHE_BYTES - 1);
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for (; i < end; i += L1_CACHE_BYTES)
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{
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asm volatile("dcache.cipa %0\n"::"r"(i):"memory");
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}
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asm volatile("fence.i":::"memory");
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}
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static void icache_inv_range(unsigned long start, unsigned long end)
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{
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unsigned long i = start & ~(L1_CACHE_BYTES - 1);
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for (; i < end; i += L1_CACHE_BYTES)
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{
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asm volatile("icache.ipa %0\n"::"r"(i):"memory");
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}
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asm volatile("fence.i":::"memory");
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}
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void awos_arch_clean_dcache(void)
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{
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asm volatile("dcache.call\n":::"memory");
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}
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void awos_arch_clean_flush_dcache(void)
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{
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asm volatile("dcache.ciall\n":::"memory");
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}
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void awos_arch_flush_dcache(void)
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{
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asm volatile("dcache.iall\n":::"memory");
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}
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void awos_arch_flush_icache(void)
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{
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asm volatile("icache.iall\n":::"memory");
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}
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void awos_arch_mems_flush_icache_region(unsigned long start, unsigned long len)
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{
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icache_inv_range(start, start + len);
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}
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void awos_arch_mems_clean_dcache_region(unsigned long start, unsigned long len)
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{
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dcache_wb_range(start, start + len);
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}
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void awos_arch_mems_clean_flush_dcache_region(unsigned long start, unsigned long len)
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{
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dcache_wbinv_range(start, start + len);
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}
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void awos_arch_mems_flush_dcache_region(unsigned long start, unsigned long len)
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{
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dcache_inv_range(start, start + len);
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}
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void awos_arch_clean_flush_cache(void)
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{
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awos_arch_clean_flush_dcache();
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awos_arch_flush_icache();
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}
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void awos_arch_clean_flush_cache_region(unsigned long start, unsigned long len)
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{
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awos_arch_mems_clean_flush_dcache_region(start, len);
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awos_arch_mems_flush_icache_region(start, len);
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}
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void awos_arch_flush_cache(void)
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{
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awos_arch_flush_dcache();
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awos_arch_flush_icache();
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}
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int check_virtual_address(unsigned long vaddr)
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{
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return 1;
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}
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void dcache_enable(void)
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{
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/*
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(0:1) CACHE_SEL=2’b11时，选中指令和数据高速缓存
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(4) INV=1时高速缓存进行无效化
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(16) BHT_INV=1时分支历史表内的数据进行无效化
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(17) TB_INV=1时分支目标缓冲器内的数据进行无效化
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*/
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//csr_write(CSR_MCOR, 0x70013);
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/*
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(0) IE=1时Icache打开
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(1) DE=1时Dcache打开
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(2) WA=1时数据高速缓存为write allocate模式 (c906不支持)
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(3) WB=1时数据高速缓存为写回模式 (c906固定为1)
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(4) RS=1时返回栈开启
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(5) BPE=1时预测跳转开启
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(6) BTB=1时分支目标预测开启
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(8) WBR=1时支持写突发传输写 （c906固定为1）
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(12) L0BTB=1时第一级分支目标预测开启
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*/
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csr_write(CSR_MHCR, 0x11ff);
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/*
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(15) MM为1时支持非对齐访问，硬件处理非对齐访问
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(16) UCME为1时，用户模式可以执行扩展的cache操作指令
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(17) CLINTEE为1时，CLINT发起的超级用户软件中断和计时器中断可以被响应
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(21) MAEE为1时MMU的pte中扩展地址属性位，用户可以配置页面的地址属性
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(22) THEADISAEE为1时可以使用C906扩展指令集
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*/
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csr_set(CSR_MXSTATUS, 0x638000);
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/*
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(2) DPLD=1，dcache预取开启
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(3,4,5,6,7) AMR=1，时，在出现连续3条缓存行的存储操作时后续连续地址的存储操作不再写入L1Cache
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(8) IPLD=1ICACHE预取开启
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(9) LPE=1循环加速开启
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(13,14) DPLD为2时，预取8条缓存行
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*/
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//csr_write(CSR_MHINT, 0x16e30c);
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csr_write(CSR_MHINT, 0x6e30c);
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}
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void dcache_disable(void)
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{
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}
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void data_sync_barrier(void)
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{
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asm volatile("fence.i":::"memory");
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}
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