834 lines
21 KiB
C
834 lines
21 KiB
C
/*
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* SUNXI NSI driver
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*
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* Copyright (C) 2015 AllWinnertech Ltd.
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* Author: xiafeng <xiafeng@allwinnertech.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/sunxi_nsi.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include <linux/hwmon.h>
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#include <linux/hwmon-sysfs.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <asm/cacheflush.h>
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#include <asm/smp_plat.h>
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#define DRIVER_NAME "NSI"
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#define DRIVER_NAME_PMU DRIVER_NAME"_PMU"
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#define MBUS_QOS_MAX 0x3
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#define for_each_ports(port) for (port = 0; port < MBUS_PMU_MAX; port++)
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/* n = 0~19 */
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#define IAG_MODE(n) (0x0010 + (0x200 * n))
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#define IAG_PRI_CFG(n) (0x0014 + (0x200 * n))
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#define IAG_INPUT_OUTPUT_CFG(n) (0x0018 + (0x200 * n))
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/* Counter n = 0 ~ 19 */
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#define MBUS_PMU_ENABLE(n) (0x00c0 + (0x200 * n))
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#define MBUS_PMU_CLR(n) (0x00c4 + (0x200 * n))
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#define MBUS_PMU_CYCLE(n) (0x00c8 + (0x200 * n))
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#define MBUS_PMU_RQ_RD(n) (0x00cc + (0x200 * n))
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#define MBUS_PMU_RQ_WR(n) (0x00d0 + (0x200 * n))
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#define MBUS_PMU_DT_RD(n) (0x00d4 + (0x200 * n))
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#define MBUS_PMU_DT_WR(n) (0x00d8 + (0x200 * n))
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#define MBUS_PMU_LA_RD(n) (0x00dc + (0x200 * n))
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#define MBUS_PMU_LA_WR(n) (0x00e0 + (0x200 * n))
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#define MBUS_PORT_MODE (MBUS_PMU_MAX + 0)
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#define MBUS_PORT_QOS (MBUS_PMU_MAX + 1)
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#define MBUS_INPUT_OUTPUT (MBUS_PMU_MAX + 2)
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#define MBUS_PORT_TIMER (MBUS_PMU_MAX + 3)
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static unsigned int total_data;
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static unsigned int total_r_data;
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static unsigned int total_w_data;
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struct sunxi_nsi_port {
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void __iomem *base;
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unsigned long phys;
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struct device_node *dn;
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int irq;
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};
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static struct sunxi_nsi_port *ports;
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static void __iomem *nsi_ctrl_base;
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static unsigned long nsi_ctrl_phys;
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static unsigned long rate;
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static DEFINE_MUTEX(nsi_seting);
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static DEFINE_MUTEX(nsi_pmureading);
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static struct clk *pclk; /* PLL clock */
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static struct clk *mclk; /* spi module clock */
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static unsigned int mod_clk;
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/**
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* nsi_port_setthd() - set a master priority
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*
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* @pri, priority
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*/
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int notrace nsi_port_setmode(enum nsi_pmu port, unsigned int mode)
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{
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unsigned int value = 0;
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if (port >= MBUS_PMU_MAX)
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return -ENODEV;
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mutex_lock(&nsi_seting);
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value = readl_relaxed(nsi_ctrl_base + IAG_MODE(port));
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value &= ~0x3;
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writel_relaxed(value | mode, nsi_ctrl_base + IAG_MODE(port));
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mutex_unlock(&nsi_seting);
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return 0;
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}
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EXPORT_SYMBOL_GPL(nsi_port_setmode);
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/**
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* nsi_port_setpri() - set a master QOS
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*
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* @qos: the qos value want to set
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*/
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int notrace nsi_port_setpri(enum nsi_pmu port, unsigned int pri)
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{
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unsigned int value;
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if (port >= MBUS_PMU_MAX)
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return -ENODEV;
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if (pri > MBUS_QOS_MAX)
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return -EPERM;
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mutex_lock(&nsi_seting);
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value = readl_relaxed(nsi_ctrl_base + IAG_PRI_CFG(port));
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value &= ~0xf;
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writel_relaxed(value | (pri << 2) | pri,
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nsi_ctrl_base + IAG_PRI_CFG(port));
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mutex_unlock(&nsi_seting);
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return 0;
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}
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EXPORT_SYMBOL_GPL(nsi_port_setpri);
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/**
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* nsi_port_setio() - set a master's qos in or out
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*
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* @wt: the wait time want to set, based on MCLK
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*/
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int notrace nsi_port_setio(enum nsi_pmu port, bool io)
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{
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unsigned int value;
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if (port >= MBUS_PMU_MAX)
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return -ENODEV;
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mutex_lock(&nsi_seting);
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value = readl_relaxed(nsi_ctrl_base + IAG_INPUT_OUTPUT_CFG(port));
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value &= ~0x1;
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writel_relaxed(value | io, nsi_ctrl_base + IAG_INPUT_OUTPUT_CFG(port));
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mutex_unlock(&nsi_seting);
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return 0;
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}
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EXPORT_SYMBOL_GPL(nsi_port_setio);
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static void nsi_pmu_disable(enum nsi_pmu port)
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{
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unsigned int value =
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readl_relaxed(nsi_ctrl_base + MBUS_PMU_ENABLE(port));
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value &= ~(0x1);
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writel_relaxed(value, nsi_ctrl_base + MBUS_PMU_ENABLE(port));
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}
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static void nsi_pmu_enable(enum nsi_pmu port)
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{
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unsigned int value =
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readl_relaxed(nsi_ctrl_base + MBUS_PMU_ENABLE(port));
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value |= (0x1);
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writel_relaxed(value, nsi_ctrl_base + MBUS_PMU_ENABLE(port));
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}
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static void nsi_pmu_clear(enum nsi_pmu port)
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{
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unsigned int value = readl_relaxed(nsi_ctrl_base + MBUS_PMU_CLR(port));
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value |= (0x1);
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writel_relaxed(value, nsi_ctrl_base + MBUS_PMU_CLR(port));
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}
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/**
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* nsi_port_set_timer() - set a master check bitwidth in pre time
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* function
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*
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* @port: index of the port to setup
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* @us
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*/
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int notrace nsi_pmu_set_timer(enum nsi_pmu port, unsigned int us)
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{
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unsigned int value, cycle;
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rate = clk_get_rate(mclk);
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/*
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*if mclk = 400MHZ, the signel time = 1000*1000*1000/(400*1000*1000)=2.5ns
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*if check the 10us, the cycle count = 10*1000ns/2.5us = 4000
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* us*1000/(1s/400Mhz) = us*1000*400000000(rate)/1000000000
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*/
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cycle = us * rate / 1000000;
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if (port >= MBUS_PMU_MAX)
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return -ENODEV;
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mutex_lock(&nsi_seting);
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value = readl_relaxed(nsi_ctrl_base + MBUS_PMU_CYCLE(port));
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value = cycle;
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writel_relaxed(value, nsi_ctrl_base + MBUS_PMU_CYCLE(port));
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/* disabled the pmu count */
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nsi_pmu_disable(port);
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/* clean the insight counter */
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nsi_pmu_clear(port);
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/* enabled the pmu count */
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nsi_pmu_enable(port);
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udelay(us);
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mutex_unlock(&nsi_seting);
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return 0;
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}
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EXPORT_SYMBOL_GPL(nsi_pmu_set_timer);
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static const struct of_device_id sunxi_nsi_matches[] = {
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#ifdef CONFIG_ARCH_SUN8I
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{.compatible = "allwinner,sun8i-nsi",},
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#endif
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#ifdef CONFIG_ARCH_SUN50I
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{.compatible = "allwinner,sun50i-nsi",},
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#endif
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{},
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};
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static int nsi_probe(void)
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{
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int ret;
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unsigned int port;
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struct device_node *np;
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struct resource res;
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struct device_node *child;
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np = of_find_matching_node(NULL, sunxi_nsi_matches);
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if (!np)
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return -ENODEV;
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ports = kcalloc(1, sizeof(*ports), GFP_KERNEL);
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if (!ports)
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return -ENOMEM;
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ret = of_address_to_resource(np, 0, &res);
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if (!ret) {
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nsi_ctrl_base = ioremap(res.start, resource_size(&res));
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nsi_ctrl_phys = res.start;
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}
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if (ret || !nsi_ctrl_base) {
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WARN(1, "unable to ioremap nsi ctrl\n");
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ret = -ENXIO;
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goto memalloc_err;
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}
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pclk = of_clk_get(np, 0);
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if (IS_ERR_OR_NULL(pclk)) {
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pr_err("Unable to acquire module clock, return %x\n",
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PTR_RET(pclk));
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return -1;
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}
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mclk = of_clk_get(np, 1);
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if (IS_ERR_OR_NULL(mclk)) {
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pr_err("Unable to acquire module clock, return %x\n",
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PTR_RET(mclk));
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return -1;
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}
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ret = of_property_read_u32(np, "clock-frequency", &mod_clk);
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if (ret) {
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pr_err("Get clock-frequency property failed\n");
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return -1;
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}
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// clk_disable_unprepare(mclk);
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ret = clk_set_parent(mclk, pclk);
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if (ret != 0) {
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pr_err("clk_set_parent() failed! return\n");
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return -1;
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}
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rate = clk_round_rate(mclk, mod_clk);
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if (clk_set_rate(mclk, rate)) {
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pr_err("clk_set_rate failed\n");
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return -1;
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}
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if (clk_prepare_enable(mclk)) {
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pr_err("Couldn't enable nsi clock\n");
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return -EBUSY;
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}
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/* the purpose freq of MBUS is 400M, has been configied by boot */
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for_each_available_child_of_node(np, child) {
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for_each_ports(port) {
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if (strcmp(child->name, get_name(port)))
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continue;
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else
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break;
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}
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#if 0
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unsigned int val;
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if (!of_property_read_u32(child, "mode", &val)) {
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nsi_port_setmode(port, val);
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}
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if (!of_property_read_u32(child, "pri", &val)) {
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nsi_port_setpri(port, val);
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}
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if (!of_property_read_u32(child, "select", &val))
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nsi_port_setio(port, val);
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#endif
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}
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/* all the port is default opened */
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/* set default bandwidth */
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/* set default QOS */
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/* set masters' request number sequency */
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/* set masters' bandwidth limit0/1/2 */
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memalloc_err:
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kfree(ports);
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return 0;
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}
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static int nsi_init_status = -EAGAIN;
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static DEFINE_MUTEX(nsi_proing);
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static int nsi_init(void)
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{
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if (nsi_init_status != -EAGAIN)
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return nsi_init_status;
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mutex_lock(&nsi_proing);
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if (nsi_init_status == -EAGAIN)
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nsi_init_status = nsi_probe();
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mutex_unlock(&nsi_proing);
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return nsi_init_status;
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}
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/**
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* To sort out early init calls ordering a helper function is provided to
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* check if the nsi driver has beed initialized. Function check if the driver
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* has been initialized, if not it calls the init function that probes
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* the driver and updates the return value.
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*/
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bool nsi_probed(void)
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{
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return nsi_init() == 0;
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}
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EXPORT_SYMBOL_GPL(nsi_probed);
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struct nsi_data {
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struct device *hwmon_dev;
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struct mutex update_lock;
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bool valid;
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unsigned long last_updated;
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int kind;
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};
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static struct nsi_data hw_nsi_pmu;
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/*
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static void nsi_pmu_set_cycle(enum nsi_pmu port, long us)
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{
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long rate = clk_get_rate(mclk);
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unsigned int cycle = us * 1000 * rate / 1000000000;
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unsigned int value = readl_relaxed(nsi_ctrl_base + MBUS_PMU_CYCLE(port));
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value = cycle;
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writel_relaxed(value, nsi_ctrl_base + MBUS_PMU_CYCLE(port));
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}
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*/
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static unsigned int nsi_read_bandwidth(struct nsi_data *data,
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enum nsi_pmu port, char *buf)
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{
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unsigned int size;
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unsigned int x, y, z, o, p, q;
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if (port == 20) {
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#if 0
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size =
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sprintf(buf,
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"%6s: total_data: %-6uMB, r_data: %-6uMB, w_data: %-6uMB\n",
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get_name(port), (total_data) / 1024 / 1024,
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total_r_data / 1024 / 1024,
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total_w_data / 1024 / 1024);
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#else
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size = sprintf(buf, "%-6u\n", total_data / 1024);
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#endif
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total_r_data = 0;
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total_w_data = 0;
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total_data = 0;
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return size;
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}
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mutex_lock(&data->update_lock);
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/* check the request read */
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x = readl_relaxed(nsi_ctrl_base + MBUS_PMU_RQ_RD(port));
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/* check the request write */
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y = readl_relaxed(nsi_ctrl_base + MBUS_PMU_RQ_WR(port));
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/* check the data read */
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z = readl_relaxed(nsi_ctrl_base + MBUS_PMU_DT_RD(port));
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/* check the data write */
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o = readl_relaxed(nsi_ctrl_base + MBUS_PMU_DT_WR(port));
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/* check the read latency */
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p = readl_relaxed(nsi_ctrl_base + MBUS_PMU_LA_RD(port));
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/* check the write latency */
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q = readl_relaxed(nsi_ctrl_base + MBUS_PMU_LA_WR(port));
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if (port != 20) {
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total_r_data += z;
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total_w_data += o;
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total_data = total_r_data + total_w_data;
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}
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/* read pmu conter */
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#if 0
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size = sprintf(buf, "r_request:%-5u w_request:%-5u r_data:%-5u \
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w_data:%-5u r_delay:%-5u w_delay:%-5u\n", x, y, z, o, p, q);
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#else
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size = sprintf(buf, "%-6u\n", (z + o) / 1024);
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#endif
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mutex_unlock(&data->update_lock);
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return size;
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}
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static unsigned int nsi_get_value(struct nsi_data *data,
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unsigned int index, char *buf)
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{
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unsigned int i, size = 0;
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unsigned long value;
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mutex_lock(&data->update_lock);
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switch (index) {
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case MBUS_PORT_MODE: //0x10 fixed limit regulator
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for_each_ports(i) {
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value = readl_relaxed(nsi_ctrl_base + IAG_MODE(i));
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size +=
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sprintf(buf + size, "master:%-8s qos_mode:%lu\n",
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get_name(i), (value & 0x3));
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}
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break;
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case MBUS_PORT_QOS: //0x14
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for_each_ports(i) {
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value = readl_relaxed(nsi_ctrl_base + IAG_PRI_CFG(i));
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size +=
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sprintf(buf + size, "master:%-8s read_priority:%lu \
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write_priority:%lu\n", get_name(i), (value >> 2), (value & 0x3));
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}
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break;
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case MBUS_INPUT_OUTPUT: //0x18
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for_each_ports(i) {
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value = readl_relaxed(nsi_ctrl_base +
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IAG_INPUT_OUTPUT_CFG(i));
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size +=
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sprintf(buf + size,
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"master:%-8s qos_sel(0-out 1-input):%lu\n",
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get_name(i), (value & 1));
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}
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break;
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case MBUS_PORT_TIMER:
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for_each_ports(i) {
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value = readl_relaxed(nsi_ctrl_base +
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MBUS_PMU_CYCLE(i));
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if (rate > 0)
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value = value * 1000000 / rate;
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size +=
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sprintf(buf + size,
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"master%-2d:%-8s timer_us:%lu\n", i,
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get_name(i), value);
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}
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break;
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default:
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/* programmer goofed */
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WARN_ON_ONCE(1);
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value = 0;
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break;
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}
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mutex_unlock(&data->update_lock);
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return size;
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}
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static ssize_t nsi_show_value(struct device *dev,
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struct device_attribute *da, char *buf)
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{
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struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
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unsigned int len;
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|
|
if (attr->index >= MBUS_PMU_MAX) {
|
|
len = nsi_get_value(&hw_nsi_pmu, attr->index, buf);
|
|
len = (len < PAGE_SIZE) ? len : PAGE_SIZE;
|
|
return len;
|
|
} else {
|
|
len = nsi_read_bandwidth(&hw_nsi_pmu, attr->index, buf);
|
|
return len;
|
|
}
|
|
/*
|
|
return snprintf(buf, PAGE_SIZE, "%u\n",
|
|
nsi_update_device(&hw_nsi_pmu, attr->index));
|
|
*/
|
|
}
|
|
|
|
static unsigned int nsi_set_value(struct nsi_data *data, unsigned int index,
|
|
enum nsi_pmu port, unsigned int val)
|
|
{
|
|
unsigned int value;
|
|
|
|
mutex_lock(&data->update_lock);
|
|
switch (index) {
|
|
case MBUS_PORT_MODE:
|
|
nsi_port_setmode(port, val);
|
|
break;
|
|
case MBUS_PORT_QOS:
|
|
nsi_port_setpri(port, val);
|
|
break;
|
|
case MBUS_INPUT_OUTPUT:
|
|
nsi_port_setio(port, val);
|
|
break;
|
|
case MBUS_PORT_TIMER:
|
|
nsi_pmu_set_timer(port, val);
|
|
break;
|
|
default:
|
|
/* programmer goofed */
|
|
WARN_ON_ONCE(1);
|
|
value = 0;
|
|
break;
|
|
}
|
|
mutex_unlock(&data->update_lock);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static ssize_t nsi_store_value(struct device *dev,
|
|
struct device_attribute *attr,
|
|
const char *buf, size_t count)
|
|
{
|
|
int nr = to_sensor_dev_attr(attr)->index;
|
|
unsigned long port, val;
|
|
unsigned char buffer[64];
|
|
unsigned char *pbuf, *pbufi;
|
|
int err;
|
|
|
|
if (strlen(buf) >= 64) {
|
|
dev_err(dev, "arguments out of range!\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
while (*buf == ' ') /* find the first unblank character */
|
|
buf++;
|
|
strncpy(buffer, buf, strlen(buf));
|
|
|
|
pbufi = buffer;
|
|
while (*pbufi != ' ') /* find the first argument */
|
|
pbufi++;
|
|
*pbufi = 0x0;
|
|
pbuf = (unsigned char *)buffer;
|
|
err = kstrtoul(pbuf, 10, &port);
|
|
if (err < 0)
|
|
return err;
|
|
if (port >= MBUS_PMU_MAX) {
|
|
dev_err(dev, "master is illegal\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
pbuf = ++pbufi;
|
|
while (*pbuf == ' ') /* remove extra space character */
|
|
pbuf++;
|
|
pbufi = pbuf;
|
|
while ((*pbufi != ' ') && (*pbufi != '\n'))
|
|
pbufi++;
|
|
*pbufi = 0x0;
|
|
|
|
err = kstrtoul(pbuf, 10, &val);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
nsi_set_value(&hw_nsi_pmu, nr, (enum nsi_pmu)port, (unsigned int)val);
|
|
|
|
return count;
|
|
}
|
|
|
|
/* CPU bandwidth of DDR channel 0 */
|
|
static SENSOR_DEVICE_ATTR(pmu_cpuddr, 0400, nsi_show_value, NULL, MBUS_PMU_CPU);
|
|
#if (defined CONFIG_ARCH_SUN50IW10)
|
|
/* GPU bandwidth of DDR channel 0 */
|
|
static SENSOR_DEVICE_ATTR(pmu_gpuddr, 0400, nsi_show_value, NULL, MBUS_PMU_GPU);
|
|
static SENSOR_DEVICE_ATTR(pmu_sd1_ddr, 0400,
|
|
nsi_show_value, NULL, MBUS_PMU_SD1);
|
|
static SENSOR_DEVICE_ATTR(pmu_mstg_ddr, 0400,
|
|
nsi_show_value, NULL, MBUS_PMU_MSTG);
|
|
static SENSOR_DEVICE_ATTR(pmu_gmac0_ddr, 0400,
|
|
nsi_show_value, NULL, MBUS_PMU_GMAC0);
|
|
static SENSOR_DEVICE_ATTR(pmu_gmac1_ddr, 0400,
|
|
nsi_show_value, NULL, MBUS_PMU_GMAC1);
|
|
static SENSOR_DEVICE_ATTR(pmu_usb0_ddr, 0400,
|
|
nsi_show_value, NULL, MBUS_PMU_USB0);
|
|
static SENSOR_DEVICE_ATTR(pmu_usb1_ddr, 0400,
|
|
nsi_show_value, NULL, MBUS_PMU_USB1);
|
|
static SENSOR_DEVICE_ATTR(pmu_ndfc_ddr, 0400,
|
|
nsi_show_value, NULL, MBUS_PMU_NDFC);
|
|
static SENSOR_DEVICE_ATTR(pmu_dmac_ddr, 0400,
|
|
nsi_show_value, NULL, MBUS_PMU_DMAC);
|
|
static SENSOR_DEVICE_ATTR(pmu_ce_ddr, 0400, nsi_show_value, NULL, MBUS_PMU_CE);
|
|
static SENSOR_DEVICE_ATTR(pmu_de0_ddr, 0400,
|
|
nsi_show_value, NULL, MBUS_PMU_DE0);
|
|
static SENSOR_DEVICE_ATTR(pmu_de1_ddr, 0400,
|
|
nsi_show_value, NULL, MBUS_PMU_DE1);
|
|
static SENSOR_DEVICE_ATTR(pmu_ve_ddr, 0400, nsi_show_value, NULL, MBUS_PMU_VE);
|
|
static SENSOR_DEVICE_ATTR(pmu_csi_ddr, 0400,
|
|
nsi_show_value, NULL, MBUS_PMU_CSI);
|
|
static SENSOR_DEVICE_ATTR(pmu_isp_ddr, 0400,
|
|
nsi_show_value, NULL, MBUS_PMU_ISP);
|
|
static SENSOR_DEVICE_ATTR(pmu_g2d_ddr, 0400,
|
|
nsi_show_value, NULL, MBUS_PMU_G2D);
|
|
static SENSOR_DEVICE_ATTR(pmu_eink_ddr, 0400,
|
|
nsi_show_value, NULL, MBUS_PMU_EINK);
|
|
static SENSOR_DEVICE_ATTR(pmu_iommu_ddr, 0400,
|
|
nsi_show_value, NULL, MBUS_PMU_IOMMU);
|
|
static SENSOR_DEVICE_ATTR(pmu_syscpu_ddr, 0400,
|
|
nsi_show_value, NULL, MBUS_PMU_SYS_CPU);
|
|
static SENSOR_DEVICE_ATTR(pmu_total_ddr, 0400,
|
|
nsi_show_value, NULL, MBUS_PMU_TOTAL);
|
|
#endif
|
|
|
|
/* get all masters' mode or set a master's mode */
|
|
static SENSOR_DEVICE_ATTR(port_mode, 0644,
|
|
nsi_show_value, nsi_store_value, MBUS_PORT_MODE);
|
|
/* get all masters' prio or set a master's prio */
|
|
static SENSOR_DEVICE_ATTR(port_prio, 0644,
|
|
nsi_show_value, nsi_store_value, MBUS_PORT_QOS);
|
|
/* get all masters' inout or set a master's inout */
|
|
static SENSOR_DEVICE_ATTR(port_select, 0644,
|
|
nsi_show_value, nsi_store_value, MBUS_INPUT_OUTPUT);
|
|
/* get all masters' sample timer or set a master's timer */
|
|
static SENSOR_DEVICE_ATTR(port_timer, 0644,
|
|
nsi_show_value, nsi_store_value, MBUS_PORT_TIMER);
|
|
|
|
/*****************************************/
|
|
/*
|
|
static SENSOR_DEVICE_ATTR(port_acs, 0644,
|
|
nsi_show_value, nsi_store_value, MBUS_PORT_ACS);
|
|
static SENSOR_DEVICE_ATTR(port_bwl0, 0644,
|
|
nsi_show_value, nsi_store_value, MBUS_PORT_BWL0);
|
|
static SENSOR_DEVICE_ATTR(port_bwl1, 0644,
|
|
nsi_show_value, nsi_store_value, MBUS_PORT_BWL1);
|
|
static SENSOR_DEVICE_ATTR(port_bwl2, 0644,
|
|
nsi_show_value, nsi_store_value, MBUS_PORT_BWL2);
|
|
static SENSOR_DEVICE_ATTR(port_bwlen, 0644,
|
|
nsi_show_value, nsi_store_value, MBUS_PORT_BWLEN);
|
|
static SENSOR_DEVICE_ATTR(port_abs_bwlen, 0644,
|
|
nsi_show_value, nsi_store_value, MBUS_PORT_ABS_BWLEN);
|
|
static SENSOR_DEVICE_ATTR(port_abs_bwl, 0644,
|
|
nsi_show_value, nsi_store_value, MBUS_PORT_ABS_BWL);
|
|
static SENSOR_DEVICE_ATTR(port_bw_satu, 0644,
|
|
nsi_show_value, nsi_store_value, MBUS_PORT_BW_SATU);
|
|
*/
|
|
/**************************************/
|
|
|
|
/* pointers to created device attributes */
|
|
static struct attribute *nsi_attributes[] = {
|
|
&sensor_dev_attr_pmu_cpuddr.dev_attr.attr,
|
|
|
|
#if (defined CONFIG_ARCH_SUN50IW10)
|
|
&sensor_dev_attr_pmu_gpuddr.dev_attr.attr,
|
|
&sensor_dev_attr_pmu_sd1_ddr.dev_attr.attr,
|
|
&sensor_dev_attr_pmu_mstg_ddr.dev_attr.attr,
|
|
&sensor_dev_attr_pmu_gmac0_ddr.dev_attr.attr,
|
|
&sensor_dev_attr_pmu_gmac1_ddr.dev_attr.attr,
|
|
&sensor_dev_attr_pmu_usb0_ddr.dev_attr.attr,
|
|
&sensor_dev_attr_pmu_usb1_ddr.dev_attr.attr,
|
|
&sensor_dev_attr_pmu_ndfc_ddr.dev_attr.attr,
|
|
&sensor_dev_attr_pmu_dmac_ddr.dev_attr.attr,
|
|
&sensor_dev_attr_pmu_ce_ddr.dev_attr.attr,
|
|
&sensor_dev_attr_pmu_de0_ddr.dev_attr.attr,
|
|
&sensor_dev_attr_pmu_de1_ddr.dev_attr.attr,
|
|
&sensor_dev_attr_pmu_ve_ddr.dev_attr.attr,
|
|
&sensor_dev_attr_pmu_csi_ddr.dev_attr.attr,
|
|
&sensor_dev_attr_pmu_isp_ddr.dev_attr.attr,
|
|
&sensor_dev_attr_pmu_g2d_ddr.dev_attr.attr,
|
|
&sensor_dev_attr_pmu_eink_ddr.dev_attr.attr,
|
|
&sensor_dev_attr_pmu_iommu_ddr.dev_attr.attr,
|
|
&sensor_dev_attr_pmu_syscpu_ddr.dev_attr.attr,
|
|
&sensor_dev_attr_pmu_total_ddr.dev_attr.attr,
|
|
#endif
|
|
|
|
&sensor_dev_attr_port_mode.dev_attr.attr,
|
|
&sensor_dev_attr_port_prio.dev_attr.attr,
|
|
&sensor_dev_attr_port_select.dev_attr.attr,
|
|
&sensor_dev_attr_port_timer.dev_attr.attr,
|
|
/*
|
|
&sensor_dev_attr_port_acs.dev_attr.attr,
|
|
&sensor_dev_attr_port_bwl0.dev_attr.attr,
|
|
&sensor_dev_attr_port_bwl1.dev_attr.attr,
|
|
&sensor_dev_attr_port_bwl2.dev_attr.attr,
|
|
&sensor_dev_attr_port_bwlen.dev_attr.attr,
|
|
&sensor_dev_attr_port_abs_bwlen.dev_attr.attr,
|
|
&sensor_dev_attr_port_abs_bwl.dev_attr.attr,
|
|
&sensor_dev_attr_port_bw_satu.dev_attr.attr,
|
|
*/
|
|
NULL,
|
|
};
|
|
|
|
static struct attribute_group nsi_group = {
|
|
.attrs = nsi_attributes,
|
|
};
|
|
|
|
static const struct attribute_group *nsi_groups[] = {
|
|
&nsi_group,
|
|
NULL,
|
|
};
|
|
|
|
static int nsi_pmu_probe(struct platform_device *pdev)
|
|
{
|
|
int ret;
|
|
|
|
hw_nsi_pmu.hwmon_dev =
|
|
devm_hwmon_device_register_with_groups(&pdev->dev, "nsi_pmu", NULL,
|
|
nsi_groups);
|
|
|
|
if (IS_ERR(hw_nsi_pmu.hwmon_dev)) {
|
|
ret = PTR_ERR(hw_nsi_pmu.hwmon_dev);
|
|
goto out_err;
|
|
}
|
|
|
|
hw_nsi_pmu.last_updated = 0;
|
|
hw_nsi_pmu.valid = 0;
|
|
mutex_init(&hw_nsi_pmu.update_lock);
|
|
|
|
return 0;
|
|
|
|
out_err:
|
|
dev_err(&(pdev->dev), "probed failed\n");
|
|
sysfs_remove_group(&pdev->dev.kobj, &nsi_group);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int nsi_pmu_remove(struct platform_device *pdev)
|
|
{
|
|
hwmon_device_unregister(hw_nsi_pmu.hwmon_dev);
|
|
sysfs_remove_group(&pdev->dev.kobj, &nsi_group);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
static int sunxi_nsi_suspend(struct device *dev)
|
|
{
|
|
dev_info(dev, "suspend okay\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sunxi_nsi_resume(struct device *dev)
|
|
{
|
|
dev_info(dev, "resume okay\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops sunxi_nsi_pm_ops = {
|
|
.suspend = sunxi_nsi_suspend,
|
|
.resume = sunxi_nsi_resume,
|
|
};
|
|
|
|
#define SUNXI_MBUS_PM_OPS (&sunxi_nsi_pm_ops)
|
|
#else
|
|
#define SUNXI_MBUS_PM_OPS NULL
|
|
#endif
|
|
|
|
static struct platform_driver nsi_pmu_driver = {
|
|
.driver = {
|
|
.name = DRIVER_NAME_PMU,
|
|
.owner = THIS_MODULE,
|
|
.pm = SUNXI_MBUS_PM_OPS,
|
|
.of_match_table = sunxi_nsi_matches,
|
|
},
|
|
.probe = nsi_pmu_probe,
|
|
.remove = nsi_pmu_remove,
|
|
};
|
|
|
|
static int __init nsi_pmu_init(void)
|
|
{
|
|
int ret;
|
|
|
|
ret = platform_driver_register(&nsi_pmu_driver);
|
|
if (ret) {
|
|
pr_err("register sunxi nsi platform driver failed\n");
|
|
goto drv_err;
|
|
}
|
|
|
|
return ret;
|
|
|
|
drv_err:
|
|
platform_driver_unregister(&nsi_pmu_driver);
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
early_initcall(nsi_init);
|
|
device_initcall(nsi_pmu_init);
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_DESCRIPTION("SUNXI NSI support");
|
|
MODULE_AUTHOR("xiafeng");
|