167 lines
5.9 KiB
C
167 lines
5.9 KiB
C
/*
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* Copyright (C) 2013 Allwinnertech, huanghuafeng <huafenghuang@allwinnertech.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Adjustable factor-based clock implementation
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*/
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#ifndef __MACH_SUNXI_CLK_SUN50IW11_H
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#define __MACH_SUNXI_CLK_SUN50IW11_H
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/io.h>
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#include "clk-factors.h"
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#define BUS_GATE2 0x0068
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#define IR0_CFG 0x00D0
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#define BUS_RST3 0x02D0
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/* PRCM PLL Register List */
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#define PLL_CPU 0x1000
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#define PLL_PERIPH0 0x1010
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#define PLL_AUDIO0 0x1020
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#define PLL_AUDIO1 0x1030
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#define PLL_PERI0PAT0 0x1110
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#define PLL_PERI0PAT1 0x1114
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#define PLL_AUDIO0PAT0 0x1120
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#define PLL_AUDIO0PAT1 0x1124
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#define PLL_AUDIO1PAT0 0x1130
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#define PLL_AUDIO1PAT1 0x1134
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/* CCMU Register List */
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#define CPU_CFG 0x0500
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#define PSI_CFG 0x0510
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#define AHB_CFG 0x0510
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#define APB1_CFG 0x0520
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#define APB2_CFG 0x0524
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#define MBUS_CFG 0x0540
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/* Accelerator */
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#define CE_CFG 0x0680
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#define CE_GATE 0x068C
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#define AIPU_CFG 0x06F0
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#define AIPU_GATE 0x06FC
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/* SYS Resource */
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#define DMA_GATE 0x070C
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#define MSGBOX_GATE 0x071C
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#define SPINLOCK_GATE 0x072C
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#define HSTIMER_GATE 0x073C
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#define AVS_GATE 0x0740
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#define DBGSYS_GATE 0x078C
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#define PSI_GATE 0x079C
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#define PWM_GATE 0x07AC
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/* Storage Medium */
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#define DRAM_CFG 0x0800
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#define MBUS_GATE 0x0804
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#define DRAM_GATE 0x080C
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#define NAND0_CFG 0x0810
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#define NAND1_CFG 0x0814
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#define NAND_GATE 0x082C
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#define SMHC0_CFG 0x0830
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#define SMHC1_CFG 0x0834
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#define SMHC_GATE 0x084C
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/* Common Interface */
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#define UART_GATE 0x090C
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#define TWI_GATE 0x091C
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#define SCR_GATE 0x093C
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#define SPI0_CFG 0x0940
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#define SPI1_CFG 0x0944
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#define SPI_GATE 0x096C
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#define GMAC0_25M_CFG 0x0970
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#define GMAC_GATE 0x097C
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#define IRRX_CFG 0x0990
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#define IRRX_GATE 0x099C
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#define IRTX_CFG 0x09C0
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#define IRTX_GATE 0x09CC
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#define I2S0_CFG 0x0A10
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#define I2S1_CFG 0x0A14
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#define I2S2_CFG 0x0A18
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#define I2S_GATE 0x0A1C
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#define SPDIF_CFG 0x0A20
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#define SPDIFRX_CFG 0x0A24
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#define SPDIF_GATE 0x0A2C
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#define USB0_CFG 0x0A70
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#define USB1_CFG 0x0A74
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#define USB_GATE 0x0A8C
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#define LEDC_CFG 0x0BF0
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#define LEDC_GATE 0x0BFC
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#define SUNXI_CLK_MAX_REG 0x0BFC
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/* PRCM Register List */
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#define CPUS_AHBS_CFG 0x0000
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#define CPUS_APBS0_CFG 0x000C
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#define CPUS_APBS1_CFG 0x0010
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#define CPUS_LOCKDG_CFG 0x0020
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#define CPUS_DG_CFG 0x0024
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#define CPUS_LPSD_CFG 0x00D0
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#define CPUS_MAD_GATE 0x00DC
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#define CPUS_GPADC_GATE 0x00EC
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#define CPUS_THS_GATE 0x00FC
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#define CPUS_DMA_GATE 0x010C
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#define CPUS_TIMER_GATE 0x011C
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#define CPUS_TWDOG_GATE 0x012C
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#define CPUS_PWM_CFG 0x0130
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#define CPUS_PWM_GATE 0x013C
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#define CODEC_ADC_CFG 0x0140
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#define CODEC_DAC_CFG 0x0144
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#define CODEC_GATE 0x014C
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#define CPUS_DMIC_CFG 0x0150
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#define CPUS_DMIC_GATE 0x015C
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#define CPUS_LRADC_GATE 0x016C
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#define CPUS_I2S0_CFG 0x0170
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#define I2S0_ASRC_CFG 0x0174
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#define CPUS_I2S1_CFG 0x0178
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#define CPUS_I2S_GATE 0x017C
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#define CPUS_UART_GATE 0x018C
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#define CPUS_TWI_GATE 0x019C
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#define CPUS_PPU_GATE 0x01AC
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#define CPUS_DSP_GATE 0x01BC
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#define CPUS_IRRX_CFG 0x01C0
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#define CPUS_IRRX_GATE 0x01CC
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#define CPUS_MSGBOX_GATE 0x01DC
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#define CPUS_SPINLOCK_GATE 0x01EC
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#define CPUS_DSP_SRAM_GATE 0x01FC
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#define CPUS_RTC_GATE 0x020C
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#define CPUS_PSARM_CFG 0x0210
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#define CPUS_PSARM_GATE 0x021C
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#define CPUS_CPUCFG_GATE 0x022C
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#define CPUS_CLK_MAX_REG 0x022C
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/* RTC Register List */
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#define LOSC_OUT_GATE 0x0060
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#define DCXO_OUT_CFG 0x0160
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#define RTC_SPI_CFG 0x0310
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#define F_N8X8_M0X2_P16x2(nv, mv, pv) (FACTOR_ALL(nv, 8, 8, 0, 0, 0, mv, 0, 2, pv, 16, 2, 0, 0, 0, 0, 0, 0))
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#define F_N8X8(nv) (FACTOR_ALL(nv, 8, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0))
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#define F_N8X8_M1X1_P16x3(nv, mv, pv) (FACTOR_ALL(nv, 8, 8, 0, 0, 0, mv, 1, 1, pv, 16, 3, 0, 0, 0, 0, 0, 0))
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#define F_N8X8_D1V1X1_D2V0X1(nv, d1v, d2v) (FACTOR_ALL(nv, 8, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, d1v, 1, 1, d2v, 0, 1))
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#define F_N8X8_D1V1X1(nv, d1v) (FACTOR_ALL(nv, 8, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, d1v, 1, 1, 0, 0, 0))
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#define F_N8X8_D1V4X2_D2V0X2(nv, d1v, d2v) (FACTOR_ALL(nv, 8, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, d1v, 4, 2, d2v, 0, 2))
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#define F_N8X8_P16X6_D1V1X1_D2V0X1(nv, pv, d1v, d2v) (FACTOR_ALL(nv, 8, 8, 0, 0, 0, 0, 0, 0, pv, 16, 6, d1v, 1, 1, d2v, 0, 1))
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#define PLLCPU(n, freq) {F_N8X8(n), freq}
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#define PLLDDR(n, d1, d2, freq) {F_N8X8_D1V1X1_D2V0X1(n, d1, d2), freq}
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#define PLLPERIPH0(n, m, p, freq) {F_N8X8_M1X1_P16x3(n, m, p), freq}
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#define PLLPERIPH1(n, d1, d2, freq) {F_N8X8_D1V1X1_D2V0X1(n, d1, d2), freq}
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#define PLLGPU(n, d1, d2, freq) {F_N8X8_D1V1X1_D2V0X1(n, d1, d2), freq}
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#define PLLVIDEO0(n, d1, freq) {F_N8X8_D1V1X1(n, d1), freq}
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#define PLLVIDEO1(n, d1, freq) {F_N8X8_D1V1X1(n, d1), freq}
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#define PLLVIDEO2(n, d1, freq) {F_N8X8_D1V1X1(n, d1), freq}
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#define PLLVE(n, d1, d2, freq) {F_N8X8_D1V1X1_D2V0X1(n, d1, d2), freq}
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#define PLLCOM(n, d1, d2, freq) {F_N8X8_D1V1X1_D2V0X1(n, d1, d2), freq}
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#define PLLAUDIO(n, p, d1, d2, freq) {F_N8X8_P16X6_D1V1X1_D2V0X1(n, p, d1, d2), freq}
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#endif
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