301 lines
13 KiB
C
301 lines
13 KiB
C
/*
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* Copyright (c) 2019-2025 Allwinner Technology Co., Ltd. ALL rights reserved.
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*
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* Allwinner is a trademark of Allwinner Technology Co.,Ltd., registered in
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* the the People's Republic of China and other countries.
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* All Allwinner Technology Co.,Ltd. trademarks are used with permission.
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*
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* DISCLAIMER
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* THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT.
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* IF YOU NEED TO INTEGRATE THIRD PARTY’S TECHNOLOGY (SONY, DTS, DOLBY, AVS OR MPEGLA, ETC.)
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* IN ALLWINNERS’SDK OR PRODUCTS, YOU SHALL BE SOLELY RESPONSIBLE TO OBTAIN
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* ALL APPROPRIATELY REQUIRED THIRD PARTY LICENCES.
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* ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS
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* COVERED UNDER ANY REQUIRED THIRD PARTY LICENSE.
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* YOU ARE SOLELY RESPONSIBLE FOR YOUR USAGE OF THIRD PARTY’S TECHNOLOGY.
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*
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*
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* THIS SOFTWARE IS PROVIDED BY ALLWINNER"AS IS" AND TO THE MAXIMUM EXTENT
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* PERMITTED BY LAW, ALLWINNER EXPRESSLY DISCLAIMS ALL WARRANTIES OF ANY KIND,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION REGARDING
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* THE TITLE, NON-INFRINGEMENT, ACCURACY, CONDITION, COMPLETENESS, PERFORMANCE
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* OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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* IN NO EVENT SHALL ALLWINNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS, OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ASM_RISCV_IO_H
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#define _ASM_RISCV_IO_H
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#include <stdint.h>
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#include <stddef.h>
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#include <stdbool.h>
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/* Generic IO read/write. These perform native-endian accesses. */
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#define __raw_writeb __raw_writeb
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static inline void __raw_writeb(uint8_t val, volatile void *addr)
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{
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asm volatile("sb %0, 0(%1)" : : "r"(val), "r"(addr));
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}
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#define __raw_writew __raw_writew
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static inline void __raw_writew(uint16_t val, volatile void *addr)
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{
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asm volatile("sh %0, 0(%1)" : : "r"(val), "r"(addr));
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}
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#define __raw_writel __raw_writel
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static inline void __raw_writel(uint32_t val, volatile void *addr)
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{
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asm volatile("sw %0, 0(%1)" : : "r"(val), "r"(addr));
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}
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#ifdef CONFIG_64BIT
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#define __raw_writeq __raw_writeq
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static inline void __raw_writeq(uint64_t val, volatile void *addr)
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{
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asm volatile("sd %0, 0(%1)" : : "r"(val), "r"(addr));
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}
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#endif
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#define __raw_readb __raw_readb
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static inline uint8_t __raw_readb(const volatile void *addr)
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{
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uint8_t val;
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asm volatile("lb %0, 0(%1)" : "=r"(val) : "r"(addr));
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return val;
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}
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#define __raw_readw __raw_readw
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static inline uint16_t __raw_readw(const volatile void *addr)
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{
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uint16_t val;
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asm volatile("lh %0, 0(%1)" : "=r"(val) : "r"(addr));
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return val;
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}
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#define __raw_readl __raw_readl
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static inline uint32_t __raw_readl(const volatile void *addr)
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{
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uint32_t val;
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asm volatile("lw %0, 0(%1)" : "=r"(val) : "r"(addr));
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return val;
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}
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#ifdef CONFIG_64BIT
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#define __raw_readq __raw_readq
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static inline uint64_t __raw_readq(const volatile void *addr)
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{
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uint64_t val;
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asm volatile("ld %0, 0(%1)" : "=r"(val) : "r"(addr));
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return val;
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}
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#endif
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#define mmiowb_set_pending() do { } while (0)
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#define cpu_to_le16(val) (val)
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#define cpu_to_le32(val) (val)
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#define cpu_to_le64(val) (val)
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#define le32_to_cpu(val) (val)
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/*
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* Unordered I/O memory access primitives. These are even more relaxed than
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* the relaxed versions, as they don't even order accesses between successive
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* operations to the I/O regions.
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*/
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#define readb_cpu(c) ({ uint8_t __r = __raw_readb(c); __r; })
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#define readw_cpu(c) ({ uint16_t __r = le16_to_cpu(__raw_readw(c)); __r; })
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#define readl_cpu(c) ({ uint32_t __r = le32_to_cpu(__raw_readl(c)); __r; })
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#define writeb_cpu(v,c) ((void)__raw_writeb((v),(c)))
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#define writew_cpu(v,c) ((void)__raw_writew((uint16_t)cpu_to_le16(v),(c)))
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#define writel_cpu(v,c) ((void)__raw_writel((uint32_t)cpu_to_le32(v),(c)))
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#ifdef CONFIG_64BIT
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#define readq_cpu(c) ({ uint64_t __r = le64_to_cpu((__le64)__raw_readq(c)); __r; })
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#define writeq_cpu(v,c) ((void)__raw_writeq((uint64_t)cpu_to_le64(v),(c)))
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#endif
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/*
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* Relaxed I/O memory access primitives. These follow the Device memory
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* ordering rules but do not guarantee any ordering relative to Normal memory
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* accesses. These are defined to order the indicated access (either a read or
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* write) with all other I/O memory accesses. Since the platform specification
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* defines that all I/O regions are strongly ordered on channel 2, no explicit
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* fences are required to enforce this ordering.
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*/
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/* FIXME: These are now the same as asm-generic */
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#define __io_rbr() do {} while (0)
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#define __io_rar() do {} while (0)
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#define __io_rbw() do {} while (0)
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#define __io_raw() do {} while (0)
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#define readb_relaxed(c) ({ uint8_t __v; __io_rbr(); __v = readb_cpu(c); __io_rar(); __v; })
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#define readw_relaxed(c) ({ uint16_t __v; __io_rbr(); __v = readw_cpu(c); __io_rar(); __v; })
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#define readl_relaxed(c) ({ uint32_t __v; __io_rbr(); __v = readl_cpu(c); __io_rar(); __v; })
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#define writeb_relaxed(v,c) ({ __io_rbw(); writeb_cpu((v),(c)); __io_raw(); })
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#define writew_relaxed(v,c) ({ __io_rbw(); writew_cpu((v),(c)); __io_raw(); })
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#define writel_relaxed(v,c) ({ __io_rbw(); writel_cpu((v),(c)); __io_raw(); })
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#ifdef CONFIG_64BIT
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#define readq_relaxed(c) ({ uint64_t __v; __io_rbr(); __v = readq_cpu(c); __io_rar(); __v; })
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#define writeq_relaxed(v,c) ({ __io_rbw(); writeq_cpu((v),(c)); __io_raw(); })
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#endif
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/*
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* I/O memory access primitives. Reads are ordered relative to any
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* following Normal memory access. Writes are ordered relative to any prior
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* Normal memory access. The memory barriers here are necessary as RISC-V
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* doesn't define any ordering between the memory space and the I/O space.
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*/
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#define __io_br() do {} while (0)
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#define __io_ar(v) __asm__ __volatile__ ("fence i,r" : : : "memory");
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#define __io_bw() __asm__ __volatile__ ("fence w,o" : : : "memory");
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#define __io_aw() mmiowb_set_pending()
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#define readb(c) ({ uint8_t __v; __io_br(); __v = readb_cpu(c); __io_ar(__v); __v; })
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#define readw(c) ({ uint16_t __v; __io_br(); __v = readw_cpu(c); __io_ar(__v); __v; })
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#define readl(c) ({ uint32_t __v; __io_br(); __v = readl_cpu(c); __io_ar(__v); __v; })
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#define writeb(v,c) ({ __io_bw(); writeb_cpu((v),(c)); __io_aw(); })
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#define writew(v,c) ({ __io_bw(); writew_cpu((v),(c)); __io_aw(); })
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#define writel(v,c) ({ __io_bw(); writel_cpu((v),(c)); __io_aw(); })
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#ifdef CONFIG_64BIT
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#define readq(c) ({ uint64_t __v; __io_br(); __v = readq_cpu(c); __io_ar(__v); __v; })
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#define writeq(v,c) ({ __io_bw(); writeq_cpu((v),(c)); __io_aw(); })
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#endif
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/*
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* I/O port access constants.
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*/
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#define IO_SPACE_LIMIT (PCI_IO_SIZE - 1)
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#define PCI_IOBASE ((void *)PCI_IO_START)
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/*
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* Emulation routines for the port-mapped IO space used by some PCI drivers.
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* These are defined as being "fully synchronous", but also "not guaranteed to
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* be fully ordered with respect to other memory and I/O operations". We're
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* going to be on the safe side here and just make them:
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* - Fully ordered WRT each other, by bracketing them with two fences. The
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* outer set contains both I/O so inX is ordered with outX, while the inner just
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* needs the type of the access (I for inX and O for outX).
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* - Ordered in the same manner as readX/writeX WRT memory by subsuming their
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* fences.
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* - Ordered WRT timer reads, so udelay and friends don't get elided by the
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* implementation.
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* Note that there is no way to actually enforce that outX is a non-posted
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* operation on RISC-V, but hopefully the timer ordering constraint is
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* sufficient to ensure this works sanely on controllers that support I/O
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* writes.
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*/
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#define __io_pbr() __asm__ __volatile__ ("fence io,i" : : : "memory");
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#define __io_par(v) __asm__ __volatile__ ("fence i,ior" : : : "memory");
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#define __io_pbw() __asm__ __volatile__ ("fence iow,o" : : : "memory");
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#define __io_paw() __asm__ __volatile__ ("fence o,io" : : : "memory");
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#define inb(c) ({ uint8_t __v; __io_pbr(); __v = readb_cpu((void*)(PCI_IOBASE + (c))); __io_par(__v); __v; })
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#define inw(c) ({ uint16_t __v; __io_pbr(); __v = readw_cpu((void*)(PCI_IOBASE + (c))); __io_par(__v); __v; })
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#define inl(c) ({ uint32_t __v; __io_pbr(); __v = readl_cpu((void*)(PCI_IOBASE + (c))); __io_par(__v); __v; })
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#define outb(v,c) ({ __io_pbw(); writeb_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); })
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#define outw(v,c) ({ __io_pbw(); writew_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); })
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#define outl(v,c) ({ __io_pbw(); writel_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); })
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#ifdef CONFIG_64BIT
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#define inq(c) ({ uint64_t __v; __io_pbr(); __v = readq_cpu((void*)(c)); __io_par(__v); __v; })
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#define outq(v,c) ({ __io_pbw(); writeq_cpu((v),(void*)(c)); __io_paw(); })
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#endif
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/*
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* Accesses from a single hart to a single I/O address must be ordered. This
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* allows us to use the raw read macros, but we still need to fence before and
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* after the block to ensure ordering WRT other macros. These are defined to
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* perform host-endian accesses so we use __raw instead of __cpu.
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*/
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#define __io_reads_ins(port, ctype, len, bfence, afence) \
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static inline void __ ## port ## len(const volatile void *addr, \
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void *buffer, \
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unsigned int count) \
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{ \
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bfence; \
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if (count) { \
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ctype *buf = buffer; \
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\
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do { \
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ctype x = __raw_read ## len(addr); \
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*buf++ = x; \
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} while (--count); \
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} \
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afence; \
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}
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#define __io_writes_outs(port, ctype, len, bfence, afence) \
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static inline void __ ## port ## len(volatile void *addr, \
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const void *buffer, \
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unsigned int count) \
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{ \
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bfence; \
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if (count) { \
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const ctype *buf = buffer; \
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\
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do { \
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__raw_write ## len(*buf++, addr); \
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} while (--count); \
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} \
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afence; \
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}
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__io_reads_ins(reads, uint8_t, b, __io_br(), __io_ar(addr))
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__io_reads_ins(reads, uint16_t, w, __io_br(), __io_ar(addr))
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__io_reads_ins(reads, uint32_t, l, __io_br(), __io_ar(addr))
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#define readsb(addr, buffer, count) __readsb(addr, buffer, count)
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#define readsw(addr, buffer, count) __readsw(addr, buffer, count)
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#define readsl(addr, buffer, count) __readsl(addr, buffer, count)
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__io_reads_ins(ins, uint8_t, b, __io_pbr(), __io_par(addr))
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__io_reads_ins(ins, uint16_t, w, __io_pbr(), __io_par(addr))
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__io_reads_ins(ins, uint32_t, l, __io_pbr(), __io_par(addr))
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#define insb(addr, buffer, count) __insb((void *)(long)addr, buffer, count)
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#define insw(addr, buffer, count) __insw((void *)(long)addr, buffer, count)
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#define insl(addr, buffer, count) __insl((void *)(long)addr, buffer, count)
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__io_writes_outs(writes, uint8_t, b, __io_bw(), __io_aw())
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__io_writes_outs(writes, uint16_t, w, __io_bw(), __io_aw())
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__io_writes_outs(writes, uint32_t, l, __io_bw(), __io_aw())
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#define writesb(addr, buffer, count) __writesb(addr, buffer, count)
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#define writesw(addr, buffer, count) __writesw(addr, buffer, count)
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#define writesl(addr, buffer, count) __writesl(addr, buffer, count)
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__io_writes_outs(outs, uint8_t, b, __io_pbw(), __io_paw())
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__io_writes_outs(outs, uint16_t, w, __io_pbw(), __io_paw())
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__io_writes_outs(outs, uint32_t, l, __io_pbw(), __io_paw())
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#define outsb(addr, buffer, count) __outsb((void *)(long)addr, buffer, count)
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#define outsw(addr, buffer, count) __outsw((void *)(long)addr, buffer, count)
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#define outsl(addr, buffer, count) __outsl((void *)(long)addr, buffer, count)
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#ifdef CONFIG_64BIT
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__io_reads_ins(reads, uint64_t, q, __io_br(), __io_ar(addr))
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#define readsq(addr, buffer, count) __readsq(addr, buffer, count)
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__io_reads_ins(ins, uint64_t, q, __io_pbr(), __io_par(addr))
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#define insq(addr, buffer, count) __insq((void *)addr, buffer, count)
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__io_writes_outs(writes, uint64_t, q, __io_bw(), __io_aw())
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#define writesq(addr, buffer, count) __writesq(addr, buffer, count)
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__io_writes_outs(outs, uint64_t, q, __io_pbr(), __io_paw())
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#define outsq(addr, buffer, count) __outsq((void *)addr, buffer, count)
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#endif
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#endif /* _ASM_RISCV_IO_H */
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