413 lines
10 KiB
ArmAsm
413 lines
10 KiB
ArmAsm
/*
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* Copyright (c) 2019-2025 Allwinner Technology Co., Ltd. ALL rights reserved.
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*
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* Allwinner is a trademark of Allwinner Technology Co.,Ltd., registered in
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* the the People's Republic of China and other countries.
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* All Allwinner Technology Co.,Ltd. trademarks are used with permission.
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*
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* DISCLAIMER
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* THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT.
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* IF YOU NEED TO INTEGRATE THIRD PARTY’S TECHNOLOGY (SONY, DTS, DOLBY, AVS OR MPEGLA, ETC.)
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* IN ALLWINNERS’SDK OR PRODUCTS, YOU SHALL BE SOLELY RESPONSIBLE TO OBTAIN
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* ALL APPROPRIATELY REQUIRED THIRD PARTY LICENCES.
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* ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS
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* COVERED UNDER ANY REQUIRED THIRD PARTY LICENSE.
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* YOU ARE SOLELY RESPONSIBLE FOR YOUR USAGE OF THIRD PARTY’S TECHNOLOGY.
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*
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*
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* THIS SOFTWARE IS PROVIDED BY ALLWINNER"AS IS" AND TO THE MAXIMUM EXTENT
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* PERMITTED BY LAW, ALLWINNER EXPRESSLY DISCLAIMS ALL WARRANTIES OF ANY KIND,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION REGARDING
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* THE TITLE, NON-INFRINGEMENT, ACCURACY, CONDITION, COMPLETENESS, PERFORMANCE
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* OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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* IN NO EVENT SHALL ALLWINNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS, OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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.section .bss
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.align 2
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.globl g_sleep_context
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.globl g_sleep_flag
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g_sleep_context:
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.space 768
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g_sleep_flag:
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.long 0
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.macro save_csr name index
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csrr t1, \name
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sw t1, \index * 4(t0)
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.endm
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.macro restore_csr name index
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lw t1, \index * 4(t0)
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csrw \name, t1
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.endm
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.macro general_reg option base
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la t0, \base
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\option x0, 0*4(t0)
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\option ra, 1*4(t0)
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\option sp, 2*4(t0)
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\option gp, 3*4(t0)
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\option tp, 4*4(t0)
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# \option t0, 5*4(t0)
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\option t1, 6*4(t0)
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\option x7, 7*4(t0)
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\option x8, 8*4(t0)
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\option x9, 9*4(t0)
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\option x10, 10*4(t0)
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\option x11, 11*4(t0)
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\option x12, 12*4(t0)
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\option x13, 13*4(t0)
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\option x14, 14*4(t0)
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\option x15, 15*4(t0)
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\option x16, 16*4(t0)
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\option x17, 17*4(t0)
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\option x18, 18*4(t0)
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\option x19, 19*4(t0)
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\option x20, 20*4(t0)
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\option x21, 21*4(t0)
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\option x22, 22*4(t0)
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\option x23, 23*4(t0)
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\option x24, 24*4(t0)
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\option x25, 25*4(t0)
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\option x26, 26*4(t0)
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\option x27, 27*4(t0)
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\option x28, 28*4(t0)
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\option x29, 29*4(t0)
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\option x30, 30*4(t0)
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\option x31, 31*4(t0)
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addi t0, t0, 32 * 4
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.endm
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.macro float_reg option base
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\option ft0, 0*8(\base)
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\option ft1, 1*8(\base)
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\option ft2, 2*8(\base)
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\option ft3, 3*8(\base)
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\option ft4, 4*8(\base)
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\option ft5, 5*8(\base)
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\option ft6, 6*8(\base)
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\option ft7, 7*8(\base)
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\option fs0, 8*8(\base)
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\option fs1, 9*8(\base)
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\option fa0, 10*8(\base)
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\option fa1, 11*8(\base)
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\option fa2, 12*8(\base)
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\option fa3, 13*8(\base)
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\option fa4, 14*8(\base)
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\option fa5, 15*8(\base)
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\option fa6, 16*8(\base)
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\option fa7, 17*8(\base)
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\option fs2, 18*8(\base)
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\option fs3, 19*8(\base)
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\option fs4, 20*8(\base)
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\option fs5, 21*8(\base)
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\option fs6, 22*8(\base)
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\option fs7, 23*8(\base)
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\option fs8, 24*8(\base)
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\option fs9, 25*8(\base)
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\option fs10, 26*8(\base)
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\option fs11, 27*8(\base)
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\option ft8, 28*8(\base)
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\option ft9, 29*8(\base)
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\option ft10, 30*8(\base)
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\option ft11, 31*8(\base)
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addi \base, \base, 8*32
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.endm
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.text
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.align 2
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.globl cpu_suspend
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.type cpu_suspend, %function
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cpu_suspend:
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# save t0, t1 value to stack
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sw t0, -4(sp)
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sw t1, -8(sp)
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# save t0
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la t0, g_sleep_context
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lw t1, -4(sp)
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sw t1, 5 * 4(t0)
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# restore t1
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lw t1, -8(sp)
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# save register excep t0
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general_reg sw g_sleep_context
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/* Save M-mode Exception Setting Register */
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save_csr mstatus 0
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save_csr mie 1
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save_csr mtvec 2
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save_csr mtvt 3
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addi t0, t0, 4*4
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/* Save M-mode Exception Handling Register */
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save_csr mscratch 0
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save_csr mepc 1
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save_csr mcause 2
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save_csr mtval 3
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save_csr mip 4
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save_csr mnxti 5
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save_csr mscratchcsw 6
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save_csr mscratchcswl 7
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addi t0, t0, 4*8
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#ifdef CONFIG_ARCH_RISCV_FPU
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float_reg fsd t0
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/* save float status register */
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save_csr fflags 0
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save_csr frm 1
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save_csr fcsr 2
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save_csr fxcr 3
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addi t0, t0, 4*4
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#endif
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/* Save M-mode Memory Protect Register */
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save_csr pmpcfg0 0
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save_csr pmpcfg1 1
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save_csr pmpcfg2 2
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save_csr pmpcfg3 3
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save_csr pmpaddr0 4
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save_csr pmpaddr1 5
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save_csr pmpaddr2 6
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save_csr pmpaddr3 7
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save_csr pmpaddr4 8
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save_csr pmpaddr5 9
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save_csr pmpaddr6 10
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save_csr pmpaddr7 11
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save_csr pmpaddr8 12
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save_csr pmpaddr9 13
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save_csr pmpaddr10 14
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save_csr pmpaddr11 15
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save_csr pmpaddr12 16
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save_csr pmpaddr13 17
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save_csr pmpaddr14 18
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save_csr pmpaddr15 19
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addi t0, t0, 4*20
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/* Save M-mode Perf and Counter Register */
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save_csr mcounteren 0
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save_csr mcountinhibit 1
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save_csr mhpmevent3 2
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save_csr mhpmevent4 3
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save_csr mhpmevent5 4
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save_csr mhpmevent6 5
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save_csr mhpmevent7 6
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save_csr mhpmevent8 7
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save_csr mhpmevent9 8
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save_csr mhpmevent10 9
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save_csr mhpmevent11 10
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save_csr mhpmevent12 11
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save_csr mhpmevent13 12
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save_csr mhpmevent14 13
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save_csr mhpmevent15 14
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save_csr mhpmevent16 15
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save_csr mhpmevent17 16
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save_csr mcycle 17
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save_csr minstret 18
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save_csr mcycleh 19
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save_csr minstreth 20
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save_csr mhpmcounter3 21
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save_csr mhpmcounter4 22
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save_csr mhpmcounter5 23
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save_csr mhpmcounter6 24
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save_csr mhpmcounter7 25
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save_csr mhpmcounter8 26
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save_csr mhpmcounter9 27
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save_csr mhpmcounter10 28
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save_csr mhpmcounter11 29
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save_csr mhpmcounter12 30
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save_csr mhpmcounter13 31
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save_csr mhpmcounter14 32
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save_csr mhpmcounter15 33
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save_csr mhpmcounter16 34
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save_csr mhpmcounter17 35
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save_csr mhpmcounter3h 36
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save_csr mhpmcounter4h 37
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save_csr mhpmcounter5h 38
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save_csr mhpmcounter6h 39
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save_csr mhpmcounter7h 40
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save_csr mhpmcounter8h 41
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save_csr mhpmcounter9h 42
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save_csr mhpmcounter10h 43
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save_csr mhpmcounter11h 44
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save_csr mhpmcounter12h 45
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save_csr mhpmcounter13h 46
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save_csr mhpmcounter14h 47
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save_csr mhpmcounter15h 48
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save_csr mhpmcounter16h 49
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save_csr mhpmcounter17h 50
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addi t0, t0, 4*51
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/* Save M-mode Control vs Status Register */
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save_csr mxstatus 0
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save_csr mhcr 1
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save_csr mhint 2
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save_csr mraddr 3
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save_csr mexstatus 4
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save_csr mnmicause 5
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save_csr mnmipc 6
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addi t0, t0, 4*7
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/* Save Debug Register */
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# save_csr dcsr 0
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# save_csr dpc 1
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/* Updata sleep flag */
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la t0, g_sleep_flag
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li t1, 1
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sw t1, 0(t0)
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/* restore the scene */
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general_reg lw g_sleep_context
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/* restore t0 value */
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lw t0, -4(sp)
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ret
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.align 2
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.globl cpu_resume
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.type cpu_resume, %function
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cpu_resume:
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/* restore general register later */
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la t0, g_sleep_context
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addi t0, t0, 4*32
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/* Save M-mode Exception Setting Register */
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restore_csr mstatus 0
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restore_csr mie 1
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restore_csr mtvec 2
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restore_csr mtvt 3
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addi t0, t0, 4*4
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/* Save M-mode Exception Handling Register */
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restore_csr mscratch 0
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restore_csr mepc 1
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restore_csr mcause 2
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restore_csr mtval 3
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restore_csr mip 4
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# restore_csr mnxti 5
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restore_csr mscratchcsw 6
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restore_csr mscratchcswl 7
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addi t0, t0, 4*8
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#ifdef CONFIG_ARCH_RISCV_FPU
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float_reg fld t0
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/* save float status register */
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restore_csr fflags 0
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restore_csr frm 1
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restore_csr fcsr 2
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restore_csr fxcr 3
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addi t0, t0, 4*4
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#endif
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/* Save M-mode Memory Protect Register */
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restore_csr pmpcfg0 0
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restore_csr pmpcfg1 1
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restore_csr pmpcfg2 2
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restore_csr pmpcfg3 3
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restore_csr pmpaddr0 4
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restore_csr pmpaddr1 5
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restore_csr pmpaddr2 6
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restore_csr pmpaddr3 7
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restore_csr pmpaddr4 8
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restore_csr pmpaddr5 9
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restore_csr pmpaddr6 10
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restore_csr pmpaddr7 11
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restore_csr pmpaddr8 12
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restore_csr pmpaddr9 13
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restore_csr pmpaddr10 14
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restore_csr pmpaddr11 15
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restore_csr pmpaddr12 16
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restore_csr pmpaddr13 17
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restore_csr pmpaddr14 18
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restore_csr pmpaddr15 19
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addi t0, t0, 4*20
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/* Save M-mode Perf and Counter Register */
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restore_csr mcounteren 0
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restore_csr mcountinhibit 1
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restore_csr mhpmevent3 2
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restore_csr mhpmevent4 3
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restore_csr mhpmevent5 4
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restore_csr mhpmevent6 5
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restore_csr mhpmevent7 6
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restore_csr mhpmevent8 7
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restore_csr mhpmevent9 8
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restore_csr mhpmevent10 9
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restore_csr mhpmevent11 10
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restore_csr mhpmevent12 11
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restore_csr mhpmevent13 12
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restore_csr mhpmevent14 13
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restore_csr mhpmevent15 14
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restore_csr mhpmevent16 15
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restore_csr mhpmevent17 16
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restore_csr mcycle 17
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restore_csr minstret 18
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restore_csr mcycleh 19
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restore_csr minstreth 20
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restore_csr mhpmcounter3 21
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restore_csr mhpmcounter4 22
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restore_csr mhpmcounter5 23
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restore_csr mhpmcounter6 24
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restore_csr mhpmcounter7 25
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restore_csr mhpmcounter8 26
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restore_csr mhpmcounter9 27
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restore_csr mhpmcounter10 28
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restore_csr mhpmcounter11 29
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restore_csr mhpmcounter12 30
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restore_csr mhpmcounter13 31
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restore_csr mhpmcounter14 32
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restore_csr mhpmcounter15 33
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restore_csr mhpmcounter16 34
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restore_csr mhpmcounter17 35
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restore_csr mhpmcounter3h 36
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restore_csr mhpmcounter4h 37
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restore_csr mhpmcounter5h 38
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restore_csr mhpmcounter6h 39
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restore_csr mhpmcounter7h 40
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restore_csr mhpmcounter8h 41
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restore_csr mhpmcounter9h 42
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restore_csr mhpmcounter10h 43
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restore_csr mhpmcounter11h 44
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restore_csr mhpmcounter12h 45
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restore_csr mhpmcounter13h 46
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restore_csr mhpmcounter14h 47
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restore_csr mhpmcounter15h 48
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restore_csr mhpmcounter16h 49
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restore_csr mhpmcounter17h 50
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addi t0, t0, 4*51
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/* Save M-mode Control vs Status Register */
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restore_csr mxstatus 0
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restore_csr mhcr 1
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restore_csr mhint 2
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restore_csr mraddr 3
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restore_csr mexstatus 4
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restore_csr mnmicause 5
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restore_csr mnmipc 6
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addi t0, t0, 4*7
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/* Restore Debug Register */
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# restore_csr dcsr 0
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# restore_csr dpc 1
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/* Updata sleep flag */
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la t0, g_sleep_flag
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sw x0, 0(t0)
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/* restore general register */
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general_reg lw g_sleep_context
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/* restore t0 register */
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sw t1, -4(sp)
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la t1, g_sleep_context
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lw t0, 5 * 4(t1)
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lw t1, -4(sp)
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ret
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