147 lines
5.4 KiB
C
147 lines
5.4 KiB
C
/*
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* (C) Copyright 2007-2015
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Jerry Wang <wangflord@allwinnertech.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __CCMU_H
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#define __CCMU_H
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#include <config.h>
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#include <arch/cpu.h>
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/* pll list */
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#define CCMU_PLL_CPUX_CTRL_REG (SUNXI_CCM_BASE + 0x00)
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#define CCMU_PLL_DDR0_CTRL_REG (SUNXI_CCM_BASE + 0x10)
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#define CCMU_PLL_DDR1_CTRL_REG (SUNXI_CCM_BASE + 0x18)
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#define CCMU_PLL_PERI0_CTRL_REG (SUNXI_CCM_BASE + 0x20)
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#define CCMU_PLL_PERI1_CTRL_REG (SUNXI_CCM_BASE + 0x28)
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#define CCMU_PLL_GPU_CTRL_REG (SUNXI_CCM_BASE + 0x30)
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#define CCMU_PLL_VIDE00_CTRL_REG (SUNXI_CCM_BASE + 0x40)
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#define CCMU_PLL_VIDE01_CTRL_REG (SUNXI_CCM_BASE + 0x48)
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#define CCMU_PLL_VIDE02_CTRL_REG (SUNXI_CCM_BASE + 0x50)
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#define CCMU_PLL_VIDE03_CTRL_REG (SUNXI_CCM_BASE + 0x68)
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#define CCMU_PLL_VE_CTRL_REG (SUNXI_CCM_BASE + 0x58)
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#define CCMU_PLL_COM_CTRL_REG (SUNXI_CCM_BASE + 0x60)
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#define CCMU_PLL_AUDIO_CTRL_REG (SUNXI_CCM_BASE + 0x78)
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#define CCMU_PLL_HSIC_CTRL_REG (SUNXI_CCM_BASE + 0x70)
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/* cfg list */
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#define CCMU_CPUX_AXI_CFG_REG (SUNXI_CCM_BASE + 0x500)
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#define CCMU_PSI_AHB1_AHB2_CFG_REG (SUNXI_CCM_BASE + 0x510)
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#define CCMU_AHB3_CFG_GREG (SUNXI_CCM_BASE + 0x51C)
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#define CCMU_APB1_CFG_GREG (SUNXI_CCM_BASE + 0x520)
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#define CCMU_APB2_CFG_GREG (SUNXI_CCM_BASE + 0x524)
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#define CCMU_MBUS_CFG_REG (SUNXI_CCM_BASE + 0x540)
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#define CCMU_CE_CLK_REG (SUNXI_CCM_BASE + 0x680)
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#define CCMU_CE_BGR_REG (SUNXI_CCM_BASE + 0x68C)
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#define CCMU_VE_CLK_REG (SUNXI_CCM_BASE + 0x690)
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#define CCMU_VE_BGR_REG (SUNXI_CCM_BASE + 0x69C)
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/*SYS*/
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#define CCMU_DMA_BGR_REG (SUNXI_CCM_BASE + 0x70C)
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#define CCMU_AVS_CLK_REG (SUNXI_CCM_BASE + 0x740)
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#define CCMU_AVS_BGR_REG (SUNXI_CCM_BASE + 0x74C)
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/*IOMMU*/
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#define CCMU_IOMMU_BGR_REG (SUNXI_CCM_BASE + 0x7bc)
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#define IOMMU_AUTO_GATING_REG (SUNXI_IOMMU_BASE + 0X40)
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/* storage */
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#define CCMU_DRAM_CLK_REG (SUNXI_CCM_BASE + 0x800)
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#define CCMU_MBUS_MST_CLK_GATING_REG (SUNXI_CCM_BASE + 0x804)
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#define CCMU_PLL_DDR_AUX_REG (SUNXI_CCM_BASE + 0x808)
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#define CCMU_DRAM_BGR_REG (SUNXI_CCM_BASE + 0x80C)
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#define CCMU_NAND_CLK_REG (SUNXI_CCM_BASE + 0x810)
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#define CCMU_NAND_BGR_REG (SUNXI_CCM_BASE + 0x82C)
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#define CCMU_SDMMC0_CLK_REG (SUNXI_CCM_BASE + 0x830)
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#define CCMU_SDMMC1_CLK_REG (SUNXI_CCM_BASE + 0x834)
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#define CCMU_SDMMC2_CLK_REG (SUNXI_CCM_BASE + 0x838)
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#define CCMU_SMHC_BGR_REG (SUNXI_CCM_BASE + 0x84c)
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/*normal interface*/
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#define CCMU_UART_BGR_REG (SUNXI_CCM_BASE + 0x90C)
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#define CCMU_TWI_BGR_REG (SUNXI_CCM_BASE + 0x91C)
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#define CCMU_SCR_BGR_REG (SUNXI_CCM_BASE + 0x93C)
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#define CCMU_SPI0_CLK_REG (SUNXI_CCM_BASE + 0x940)
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#define CCMU_SPI1_CLK_REG (SUNXI_CCM_BASE + 0x944)
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#define CCMU_SPI_BGR_CLK_REG (SUNXI_CCM_BASE + 0x96C)
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#define CCMU_USB0_CLK_REG (SUNXI_CCM_BASE + 0xA70)
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#define CCMU_USB_BGR_REG (SUNXI_CCM_BASE + 0xA8C)
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/*DMA*/
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#define DMA_GATING_BASE CCMU_DMA_BGR_REG
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#define DMA_GATING_PASS (1)
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#define DMA_GATING_BIT (0)
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/*CE*/
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#define CE_CLK_SRC_MASK (0x1)
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#define CE_CLK_SRC_SEL_BIT (24)
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#define CE_CLK_SRC (0x01)
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#define CE_CLK_DIV_RATION_N_BIT (8)
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#define CE_CLK_DIV_RATION_N_MASK (0x3)
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#define CE_CLK_DIV_RATION_N (0)
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#define CE_CLK_DIV_RATION_M_BIT (0)
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#define CE_CLK_DIV_RATION_M_MASK (0xF)
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#define CE_CLK_DIV_RATION_M (2)
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#define CE_SCLK_ONOFF_BIT (31)
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#define CE_SCLK_ON (1)
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#define CE_GATING_BASE CCMU_CE_BGR_REG
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#define CE_GATING_PASS (1)
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#define CE_GATING_BIT (0)
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#define CE_RST_REG_BASE CCMU_CE_BGR_REG
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#define CE_RST_BIT (16)
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#define CE_DEASSERT (1)
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/*gpadc gate and reset reg*/
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#define CCMU_GPADC_BGR_REG (SUNXI_CCM_BASE + 0x09EC)
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/*lpadc gate and reset reg*/
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#define CCMU_LRADC_BGR_REG (SUNXI_CCM_BASE + 0x0A9C)
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/* ehci */
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#define BUS_CLK_GATING_REG 0x60
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#define BUS_SOFTWARE_RESET_REG 0x2c0
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#define USBPHY_CONFIG_REG 0xcc
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#define USBEHCI0_RST_BIT 24
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#define USBEHCI0_GATIING_BIT 24
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#define USBPHY0_RST_BIT 0
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#define USBPHY0_SCLK_GATING_BIT 8
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#define USBEHCI1_RST_BIT 25
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#define USBEHCI1_GATIING_BIT 25
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#define USBPHY1_RST_BIT 1
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#define USBPHY1_SCLK_GATING_BIT 9
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#endif
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