187 lines
6.0 KiB
C
187 lines
6.0 KiB
C
/*
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* (C) Copyright 2007-2015
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Jerry Wang <wangflord@allwinnertech.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __CCMU_H
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#define __CCMU_H
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#include <config.h>
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#include <arch/cpu.h>
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/* pll list */
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#define CCMU_PLL_CPUX_CTRL_REG (SUNXI_CCM_BASE + 0x00)
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#define CCMU_PLL_C0CPUX_CTRL_REG CCMU_PLL_CPUX_CTRL_REG
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#define CCMU_PLL_C1CPUX_CTRL_REG (SUNXI_CCM_BASE + 0x04)
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#define CCMU_PLL_AUDIO_CTRL_REG (SUNXI_CCM_BASE + 0x08)
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#define CCMU_PLL_VIDEO0_CTRL_REG (SUNXI_CCM_BASE + 0x10)
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#define CCMU_PLL_VE_CTRL_REG (SUNXI_CCM_BASE + 0x18)
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#define CCMU_PLL_DDR0_CTRL_REG (SUNXI_CCM_BASE + 0x20)
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#define CCMU_PLL_PERIPH0_CTRL_REG (SUNXI_CCM_BASE + 0x28)
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#define CCMU_PLL_PERIPH1_CTRL_REG (SUNXI_CCM_BASE + 0x2C)
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#define CCMU_PLL_VIDEO1_CTRL_REG (SUNXI_CCM_BASE + 0x30)
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#define CCMU_PLL_GPU_CTRL_REG (SUNXI_CCM_BASE + 0x38)
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#define CCMU_PLL_MIPI_CTRL_REG (SUNXI_CCM_BASE + 0x40)
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#define CCMU_PLL_HSIC_CTRL_REG (SUNXI_CCM_BASE + 0x44)
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#define CCMU_PLL_DE_CTRL_REG (SUNXI_CCM_BASE + 0x48)
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#define CCMU_PLL_DDR1_CTRL_REG (SUNXI_CCM_BASE + 0x4C)
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/* new mode for pll lock */
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#define CCMU_PLL_LOCK_CTRL_REG (SUNXI_CCM_BASE + 0x320)
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#define LOCK_EN_PLL_CPUX (1 << 0)
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#define LOCK_EN_PLL_AUDIO (1 << 1)
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#define LOCK_EN_PLL_VIDEO0 (1 << 2)
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#define LOCK_EN_PLL_VE (1 << 3)
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#define LOCK_EN_PLL_DDR0 (1 << 4)
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#define LOCK_EN_PLL_PERIPH0 (1 << 5)
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#define LOCK_EN_PLL_VIDEO1 (1 << 6)
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#define LOCK_EN_PLL_GPU (1 << 7)
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#define LOCK_EN_PLL_MIPI (1 << 8)
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#define LOCK_EN_PLL_HSIC (1 << 9)
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#define LOCK_EN_PLL_DE (1 << 10)
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#define LOCK_EN_PLL_DDR1 (1 << 11)
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#define LOCK_EN_PLL_PERIPH1 (1 << 12)
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#define LOCK_EN_NEW_MODE (1 << 28)
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/* cfg list */
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#define CCMU_CPUX_AXI_CFG_REG (SUNXI_CCM_BASE + 0x50)
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#define CCMU_AHB1_APB1_CFG_REG (SUNXI_CCM_BASE + 0x54)
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#define CCMU_APB2_CFG_GREG (SUNXI_CCM_BASE + 0x58)
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#define CCMU_AHB2_CFG_GREG (SUNXI_CCM_BASE + 0x5C)
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/* gate list */
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#define CCMU_BUS_CLK_GATING_REG0 (SUNXI_CCM_BASE + 0x60)
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#define CCMU_BUS_CLK_GATING_REG1 (SUNXI_CCM_BASE + 0x64)
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#define CCMU_BUS_CLK_GATING_REG2 (SUNXI_CCM_BASE + 0x68)
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#define CCMU_BUS_CLK_GATING_REG3 (SUNXI_CCM_BASE + 0x6C)
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#define CCMU_BUS_CLK_GATING_REG4 (SUNXI_CCM_BASE + 0x70)
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#define CCMU_CCI400_CFG_REG (SUNXI_CCM_BASE + 0x78)
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/* module list */
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#define CCMU_NAND0_CLK_REG (SUNXI_CCM_BASE + 0x80)
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#define CCMU_SDMMC0_CLK_REG (SUNXI_CCM_BASE + 0x88)
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#define CCMU_SDMMC1_CLK_REG (SUNXI_CCM_BASE + 0x8C)
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#define CCMU_SDMMC2_CLK_REG (SUNXI_CCM_BASE + 0x90)
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#define CCMU_SDMMC3_CLK_REG (SUNXI_CCM_BASE + 0x94)
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#define CCMU_CE_CLK_REG (SUNXI_CCM_BASE + 0x9C)
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#define CCMU_SPI0_SCLK_CTRL (SUNXI_CCM_BASE + 0xA0)
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#define CCMU_USBPHY_CLK_REG (SUNXI_CCM_BASE + 0xCC)
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#define CCMU_DRAM_CLK_REG (SUNXI_CCM_BASE + 0xF4)
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#define CCMU_PLL_DDR_CFG_REG (SUNXI_CCM_BASE + 0xF8)
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#define CCMU_MBUS_RST_REG (SUNXI_CCM_BASE + 0xFC)
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#define CCMU_DRAM_CLK_GATING_REG (SUNXI_CCM_BASE + 0x100)
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#define CCMU_AVS_CLK_REG (SUNXI_CCM_BASE + 0x144)
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#define CCMU_MBUS_CLK_REG (SUNXI_CCM_BASE + 0x15C)
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#define CCMU_PLL_STB_STATUS_REG (SUNXI_CCM_BASE + 0x20C)
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#define CCMU_PLL_C0CPUX_BIAS_REG (SUNXI_CCM_BASE + 0x220)
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/*gate rst list*/
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#define CCMU_BUS_SOFT_RST_REG0 (SUNXI_CCM_BASE + 0x2C0)
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#define CCMU_BUS_SOFT_RST_REG1 (SUNXI_CCM_BASE + 0x2C4)
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#define CCMU_BUS_SOFT_RST_REG2 (SUNXI_CCM_BASE + 0x2C8)
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#define CCMU_BUS_SOFT_RST_REG3 (SUNXI_CCM_BASE + 0x2D0)
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#define CCMU_BUS_SOFT_RST_REG4 (SUNXI_CCM_BASE + 0x2D8)
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#define CCMU_SEC_SWITCH_REG (SUNXI_CCM_BASE + 0x2F0)
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#define CCMU_AHB1_RST_REG0 (CCMU_BUS_SOFT_RST_REG0)
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#define CCMU_AHB1_GATE0_CTRL (CCMU_BUS_CLK_GATING_REG0)
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#define CCMU_PLL_PERI0_CTRL_REG CCMU_PLL_PERIPH0_CTRL_REG
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/* #define CCMU_AHB1_RST_REG0 (SUNXI_CCM_BASE+0x02C0) */
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#define CCMU_AHB1_RST_REG1 (SUNXI_CCM_BASE + 0x02C4)
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#define CCMU_AHB1_RST_REG2 (SUNXI_CCM_BASE + 0x02C8)
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#define CCMU_APB1_RST_REG (SUNXI_CCM_BASE + 0x02D0)
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/*CE*/
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#define CE_CLK_SRC_MASK (0x3)
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#define CE_CLK_SRC_SEL_BIT (24)
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#define CE_CLK_SRC (0x01)
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#define CE_CLK_DIV_RATION_N_BIT (16)
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#define CE_CLK_DIV_RATION_N_MASK (0x3)
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#define CE_CLK_DIV_RATION_N (0)
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#define CE_CLK_DIV_RATION_M_BIT (0)
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#define CE_CLK_DIV_RATION_M_MASK (0xF)
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#define CE_CLK_DIV_RATION_M (3)
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#define CE_SCLK_ONOFF_BIT (31)
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#define CE_SCLK_ON (1)
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#define CE_GATING_BASE CCMU_BUS_CLK_GATING_REG0
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#define CE_GATING_PASS (1)
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#define CE_GATING_BIT (5)
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#define CE_RST_REG_BASE CCMU_BUS_SOFT_RST_REG0
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#define CE_RST_BIT (5)
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#define CE_DEASSERT (1)
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/*DMA*/
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#define DMA_GATING_BASE CCMU_BUS_CLK_GATING_REG0
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#define DMA_GATING_PASS (1)
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#define DMA_GATING_BIT (6)
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/*for other file ,use before define*/
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#define CCM_AVS_SCLK_CTRL (CCMU_AVS_CLK_REG)
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#define CCM_AHB1_GATE0_CTRL (CCMU_BUS_CLK_GATING_REG0)
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#define CCM_AHB1_RST_REG0 (CCMU_BUS_SOFT_RST_REG0)
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/* clock ID */
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#define AXI_BUS (0)
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#define AHB1_BUS0 (1)
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#define AHB1_BUS1 (2)
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#define AHB1_LVDS (3)
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#define APB1_BUS0 (4)
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#define APB2_BUS0 (5)
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/* ehci */
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#define BUS_CLK_GATING_REG 0x60
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#define BUS_SOFTWARE_RESET_REG 0x2c0
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#define USBPHY_CONFIG_REG 0xcc
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#define USBEHCI0_RST_BIT 24
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#define USBEHCI0_GATIING_BIT 24
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#define USBPHY0_RST_BIT 0
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#define USBPHY0_SCLK_GATING_BIT 8
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#define USBEHCI1_RST_BIT 25
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#define USBEHCI1_GATIING_BIT 25
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#define USBPHY1_RST_BIT 1
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#define USBPHY1_SCLK_GATING_BIT 9
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#define SPI3_CKID ((AHB1_BUS0 << 8) | 23)
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#define SPI2_CKID ((AHB1_BUS0 << 8) | 22)
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#define SPI1_CKID ((AHB1_BUS0 << 8) | 21)
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#define SPI0_CKID ((AHB1_BUS0 << 8) | 20)
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/* SPI CONFIG */
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#define SPI_RST_OFFSET (20)
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#define SPI_GATING_OFFSET (20)
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#define CCMU_SPI0_SCLK_CTRL (SUNXI_CCM_BASE + 0xA0)
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#define CCMU_SPI1_SCLK_CTRL (SUNXI_CCM_BASE + 0xA4)
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#endif
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