192 lines
8.1 KiB
C
192 lines
8.1 KiB
C
/*
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* (C) Copyright 2018
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* wangwei@allwinnertech.com
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*/
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#ifndef _TZASC_SMC_H_
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#define _TZASC_SMC_H_
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#include <config.h>
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#include <arch/cpu.h>
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#if defined(CONFIG_ARCH_SUN50IW3) || defined(CONFIG_ARCH_SUN8IW18) || \
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defined(CONFIG_ARCH_SUN50IW9) || defined(CONFIG_ARCH_SUN8IW15) || \
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defined(CONFIG_ARCH_SUN50IW11) || defined(CONFIG_ARCH_SUN50IW5)
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#define SMC_CONFIG_REG (SUNXI_SMC_BASE + 0x0000)
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#define SMC_ACTION_REG (SUNXI_SMC_BASE + 0x0004)
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#define SMC_LD_RANGE_REG (SUNXI_SMC_BASE + 0x0008)
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#define SMC_LD_SELECT_REG (SUNXI_SMC_BASE + 0x000c)
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#define SMC_INT_STATUS_REG (SUNXI_SMC_BASE + 0x0010)
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#define SMC_INT_CLEAR_REG (SUNXI_SMC_BASE + 0x0014)
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#define SMC_FAIL_ADDR_REG (SUNXI_SMC_BASE + 0x0020)
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#define SMC_FAIL_CTRL_REG (SUNXI_SMC_BASE + 0x0028)
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#define SMC_FAIL_ID_REG (SUNXI_SMC_BASE + 0x002c)
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#define SMC_SPECU_CTRL_REG (SUNXI_SMC_BASE + 0x0030)
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#define SMC_INVER_EN_REG (SUNXI_SMC_BASE + 0x0034)
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#define SMC_DRM_MATER0_EN_REG (SUNXI_SMC_BASE + 0x0050)
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#define SMC_DRM_MATER1_EN_REG (SUNXI_SMC_BASE + 0x0054)
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#define SMC_DRM_ILLACCE_REG (SUNXI_SMC_BASE + 0x0058)
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#define SMC_MST0_BYP_REG (SUNXI_SMC_BASE + 0x0070)
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#define SMC_MST1_BYP_REG (SUNXI_SMC_BASE + 0x0074)
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#define SMC_MST2_BYP_REG (SUNXI_SMC_BASE + 0x0078)
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#define SMC_MST0_SEC_REG (SUNXI_SMC_BASE + 0x0080)
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#define SMC_MST1_SEC_REG (SUNXI_SMC_BASE + 0x0084)
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#define SMC_MST2_SEC_REG (SUNXI_SMC_BASE + 0x0088)
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#define SMC_MST0_ATTR_REG (SUNXI_SMC_BASE + 0x0090)
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#define SMC_MST1_ATTR_REG (SUNXI_SMC_BASE + 0x0094)
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#define SMC_MST2_ATTR_REG (SUNXI_SMC_BASE + 0x0098)
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#define DRM_BITMAP_CTRL_REG (SUNXI_SMC_BASE + 0x00A0)
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#define DRM_BITMAP_VAL_REG (SUNXI_SMC_BASE + 0x00A4)
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#define DRM_BITMAP_SEL_REG (SUNXI_SMC_BASE + 0x00A8)
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#define DRM_ERROR_REG (SUNXI_SMC_BASE + 0x00AC)
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#define DRM_GPU_HW_RST_REG (SUNXI_SMC_BASE + 0x00B0)
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#define DRM_VERSION_REG (SUNXI_SMC_BASE + 0x00F0)
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#define SMC_REGIN_SETUP_LOW_REG(x) (SUNXI_SMC_BASE + 0x100 + 0x10*(x))
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#define SMC_REGIN_SETUP_HIGH_REG(x) (SUNXI_SMC_BASE + 0x104 + 0x10*(x))
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#define SMC_REGIN_ATTRIBUTE_REG(x) (SUNXI_SMC_BASE + 0x108 + 0x10*(x))
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#elif defined(CFG_SUNXI_SMC_10)
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#define SMC_CONFIG_REG (SUNXI_SMC_BASE + 0x0000)
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#define SMC_ACTION_REG (SUNXI_SMC_BASE + 0x0004)
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#define SMC_LKDW_RANGE_REG (SUNXI_SMC_BASE + 0x0008)
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#define SMC_LKDW_SELECT_REG (SUNXI_SMC_BASE + 0x000c)
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#define SMC_INT_STATUS_REG (SUNXI_SMC_BASE + 0x0010)
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#define SMC_INT_CLEAR_REG (SUNXI_SMC_BASE + 0x0014)
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#define SMC_MASTER_BYPASS0_REG (SUNXI_SMC_BASE + 0x0018)
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#define SMC_MASTER_SECURITY0_REG (SUNXI_SMC_BASE + 0x001c)
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#define SMC_FAIL_ADDR_REG (SUNXI_SMC_BASE + 0x0020)
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#define SMC_FAIL_CTRL_REG (SUNXI_SMC_BASE + 0x0028)
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#define SMC_FAIL_ID_REG (SUNXI_SMC_BASE + 0x002c)
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#define SMC_SPECULATION_CTRL_REG (SUNXI_SMC_BASE + 0x0030)
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#define SMC_INVER_EN_REG (SUNXI_SMC_BASE + 0x0034)
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#define SMC_MST_ATTRI_REG (SUNXI_SMC_BASE + 0x0048)
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#define SMC_DRAM_EN_REG (SUNXI_SMC_BASE + 0x0050)
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#define SMC_DRAM_ILLEGAL_ACCESS0_REG (SUNXI_SMC_BASE + 0x0058)
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#define SMC_LOW_SADDR_REG (SUNXI_SMC_BASE + 0x0060)
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#define SMC_LOW_EADDR_REG (SUNXI_SMC_BASE + 0x0068)
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#define SMC_REGIN_SETUP_LOW_REG(x) (SUNXI_SMC_BASE + 0x100 + 0x10*(x))
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#define SMC_REGIN_SETUP_HIGH_REG(x) (SUNXI_SMC_BASE + 0x104 + 0x10*(x))
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#define SMC_REGIN_ATTRIBUTE_REG(x) (SUNXI_SMC_BASE + 0x108 + 0x10*(x))
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#elif defined(CFG_SUNXI_SMC_11)
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#define SMC_CONFIG_REG (SUNXI_SMC_BASE + 0x0000)
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#define SMC_ACTION_REG (SUNXI_SMC_BASE + 0x0004)
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#define SMC_LD_RANGE_REG (SUNXI_SMC_BASE + 0x0008)
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#define SMC_LD_SELECT_REG (SUNXI_SMC_BASE + 0x000c)
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#define SMC_INT_STATUS_REG (SUNXI_SMC_BASE + 0x0010)
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#define SMC_INT_CLEAR_REG (SUNXI_SMC_BASE + 0x0014)
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#define SMC_FAIL_ADDR_REG (SUNXI_SMC_BASE + 0x0020)
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#define SMC_FAIL_CTRL_REG (SUNXI_SMC_BASE + 0x0028)
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#define SMC_FAIL_ID_REG (SUNXI_SMC_BASE + 0x002c)
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#define SMC_SPECU_CTRL_REG (SUNXI_SMC_BASE + 0x0030)
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#define SMC_INVER_EN_REG (SUNXI_SMC_BASE + 0x0034)
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#define SMC_DRM_MATER0_EN_REG (SUNXI_SMC_BASE + 0x0050)
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#define SMC_DRM_MATER1_EN_REG (SUNXI_SMC_BASE + 0x0054)
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#define SMC_DRM_ILLACCE_REG (SUNXI_SMC_BASE + 0x0058)
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#define SMC_DRM_STATADDR_REG0 (SUNXI_SMC_BASE + 0x0060)
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#define SMC_DRM_STATADDR_REG1 (SUNXI_SMC_BASE + 0x0064)
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#define SMC_DRM_ENDADDR_REG0 (SUNXI_SMC_BASE + 0x0068)
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#define SMC_DRM_ENDADDR_REG1 (SUNXI_SMC_BASE + 0x006C)
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#define SMC_MST0_BYP_REG (SUNXI_SMC_BASE + 0x0070)
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#define SMC_MST1_BYP_REG (SUNXI_SMC_BASE + 0x0074)
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#define SMC_MST2_BYP_REG (SUNXI_SMC_BASE + 0x0078)
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#define SMC_MST0_SEC_REG (SUNXI_SMC_BASE + 0x0080)
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#define SMC_MST1_SEC_REG (SUNXI_SMC_BASE + 0x0084)
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#define SMC_MST2_SEC_REG (SUNXI_SMC_BASE + 0x0088)
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#define SMC_MST0_ATTR_REG (SUNXI_SMC_BASE + 0x0090)
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#define SMC_MST1_ATTR_REG (SUNXI_SMC_BASE + 0x0094)
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#define SMC_MST2_ATTR_REG (SUNXI_SMC_BASE + 0x0098)
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#define DRM_VERSION_REG (SUNXI_SMC_BASE + 0x00F0)
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#define SMC_REGIN_SETUP_LOW_REG(x) (SUNXI_SMC_BASE + 0x100 + 0x10*(x))
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#define SMC_REGIN_SETUP_HIGH_REG(x) (SUNXI_SMC_BASE + 0x104 + 0x10*(x))
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#define SMC_REGIN_ATTRIBUTE_REG(x) (SUNXI_SMC_BASE + 0x108 + 0x10*(x))
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#elif defined(CFG_SUNXI_SMC_30)
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#define SMC_CONFIG_REG (SUNXI_SMC_BASE + 0x0000)
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#define SMC_ACTION_REG (SUNXI_SMC_BASE + 0x0004)
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#define SMC_LKDW_RANGE_REG (SUNXI_SMC_BASE + 0x0008)
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#define SMC_LKDW_SELECT_REG (SUNXI_SMC_BASE + 0x000c)
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#define SMC_INT_STATUS_REG (SUNXI_SMC_BASE + 0x0010)
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#define SMC_INT_CLEAR_REG (SUNXI_SMC_BASE + 0x0014)
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#define SMC_FAIL_ADDR_REG (SUNXI_SMC_BASE + 0x0020)
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#define SMC_FAIL_CTRL_REG (SUNXI_SMC_BASE + 0x0028)
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#define SMC_FAIL_ID_REG (SUNXI_SMC_BASE + 0x002c)
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#define SMC_SPECULATION_CTRL_REG (SUNXI_SMC_BASE + 0x0030)
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#define SMC_DRAM_EN_REG (SUNXI_SMC_BASE + 0x0038)
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#define SMC_GPU_EN_REG (SUNXI_SMC_BASE + 0x0054)
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#define SMC_DRAM_ILLEGAL_ACCESS0_REG (SUNXI_SMC_BASE + 0x0058)
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#define SMC_LOW_SADDR_REG (SUNXI_SMC_BASE + 0x0060)
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#define SMC_LOW_EADDR_REG (SUNXI_SMC_BASE + 0x0064)
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#define SMC_BITMAP_LOW_SADDR_REG (SUNXI_SMC_BASE + 0x0068)
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#define SMC_BITMAP_LOW_EADDR_REG (SUNXI_SMC_BASE + 0x006c)
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#define SMC_MST0_BYP_REG (SUNXI_SMC_BASE + 0x0070)
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#define SMC_MST1_BYP_REG (SUNXI_SMC_BASE + 0x0074)
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#define SMC_MST2_BYP_REG (SUNXI_SMC_BASE + 0x0078)
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#define SMC_MST0_SEC_REG (SUNXI_SMC_BASE + 0x0080)
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#define SMC_MST1_SEC_REG (SUNXI_SMC_BASE + 0x0084)
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#define SMC_MST2_SEC_REG (SUNXI_SMC_BASE + 0x0088)
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#define SMC_MST0_ATTR_REG (SUNXI_SMC_BASE + 0x0090)
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#define SMC_MST1_ATTR_REG (SUNXI_SMC_BASE + 0x0094)
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#define SMC_MST2_ATTR_REG (SUNXI_SMC_BASE + 0x0098)
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#define DRM_GPU_HW_RST_REG (SUNXI_SMC_BASE + 0x00B0)
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#define DRM_VERSION_REG (SUNXI_SMC_BASE + 0x00F0)
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#define SMC_REGIN_SETUP_LOW_REG(x) (SUNXI_SMC_BASE + 0x100 + 0x10*(x))
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#define SMC_REGIN_SETUP_HIGH_REG(x) (SUNXI_SMC_BASE + 0x104 + 0x10*(x))
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#define SMC_REGIN_ATTRIBUTE_REG(x) (SUNXI_SMC_BASE + 0x108 + 0x10*(x))
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#define SMC_BMR_SRAM (SUNXI_SMC_BASE + 0x1000)
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#define SMC_BMR_SRAM_SIZE (0x8000)
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#else
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#error "Unsupported plat"
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#endif
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#ifndef __ASSEMBLY__
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struct sec_mem_region {
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u64 startAddr;
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u64 size;
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};
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/*
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* sec_mem_map is platform related
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* define in platform related board.c
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*/
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extern struct sec_mem_region sec_mem_map[];
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int sunxi_smc_config(struct sec_mem_region *sec_mem_map);
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int sunxi_drm_config(u32 dram_end, u32 drm_region_size);
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#endif
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#endif /* #ifndef _TZASC_SMC_H_ */
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