46 lines
1.0 KiB
C
46 lines
1.0 KiB
C
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/*
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* Endian independent macros for shifting bytes within registers.
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*/
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#ifndef __ARMEB__
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#define pull lsr
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#define push lsl
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#define get_byte_0 lsl #0
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#define get_byte_1 lsr #8
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#define get_byte_2 lsr #16
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#define get_byte_3 lsr #24
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#define put_byte_0 lsl #0
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#define put_byte_1 lsl #8
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#define put_byte_2 lsl #16
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#define put_byte_3 lsl #24
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#else
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#define pull lsl
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#define push lsr
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#define get_byte_0 lsr #24
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#define get_byte_1 lsr #16
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#define get_byte_2 lsr #8
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#define get_byte_3 lsl #0
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#define put_byte_0 lsl #24
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#define put_byte_1 lsl #16
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#define put_byte_2 lsl #8
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#define put_byte_3 lsl #0
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#endif
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/*
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* Data preload for architectures that support it
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*/
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#if defined(__ARM_ARCH_5E__) || defined(__ARM_ARCH_5TE__) || \
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defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) || \
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defined(__ARM_ARCH_6T2__) || defined(__ARM_ARCH_6Z__) || \
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defined(__ARM_ARCH_6ZK__) || defined(__ARM_ARCH_7A__) || \
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defined(__ARM_ARCH_7R__)
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#define PLD(code...) code
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#else
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#define PLD(code...)
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#endif
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/*
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* Cache alligned
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*/
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#define CALGN(code...) code
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