466 lines
15 KiB
C
466 lines
15 KiB
C
/*
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* (C) Copyright 2013-2016
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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*
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*/
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/*
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* (C) Copyright 2007-2012
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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*
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* Description: MMC driver for general mmc operations
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* Author: Aaron <leafy.myeh@allwinnertech.com>
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* Date: 2012-2-3 14:18:18
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*/
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#ifndef _MMC_H_
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#define _MMC_H_
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#include <linux/types.h>
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#define SD_VERSION_SD 0x20000
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#define SD_VERSION_2 (SD_VERSION_SD | 0x20)
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#define SD_VERSION_1_0 (SD_VERSION_SD | 0x10)
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#define SD_VERSION_1_10 (SD_VERSION_SD | 0x1a)
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#define MMC_VERSION_MMC 0x10000
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#define MMC_VERSION_UNKNOWN (MMC_VERSION_MMC)
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#define MMC_VERSION_1_2 (MMC_VERSION_MMC | 0x12)
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#define MMC_VERSION_1_4 (MMC_VERSION_MMC | 0x14)
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#define MMC_VERSION_2_2 (MMC_VERSION_MMC | 0x22)
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#define MMC_VERSION_3 (MMC_VERSION_MMC | 0x30)
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#define MMC_VERSION_4 (MMC_VERSION_MMC | 0x40)
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#define MMC_VERSION_4_1 (MMC_VERSION_MMC | 0x41)
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#define MMC_VERSION_4_2 (MMC_VERSION_MMC | 0x42)
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#define MMC_VERSION_4_3 (MMC_VERSION_MMC | 0x43)
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#define MMC_VERSION_4_41 (MMC_VERSION_MMC | 0x44)
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#define MMC_VERSION_4_5 (MMC_VERSION_MMC | 0x45)
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#define MMC_VERSION_5_0 (MMC_VERSION_MMC | 0x50)
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#define MMC_VERSION_5_1 (MMC_VERSION_MMC | 0x51)
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#define MMC_MODE_HS (1 << 0) /* can run at 26MHz -- DS26_SDR12*/
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#define MMC_MODE_HS_52MHz (1 << 1) /* can run at 52MHz with SDR mode -- HSSDR52_SDR25 */
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#define MMC_MODE_4BIT (1 << 2)
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#define MMC_MODE_8BIT (1 << 3)
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#define MMC_MODE_SPI (1 << 4)
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#define MMC_MODE_HC (1 << 5)
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#define MMC_MODE_DDR_52MHz (1 << 6) /* can run at 52Mhz with DDR mode -- HSDDR52_DDR50 */
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#define MMC_MODE_HS200 (1 << 7) /* can run at 200/208MHz with SDR mode -- HS200_SDR104*/
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#define MMC_MODE_HS400 (1 << 8) /* can run at 200MHz with DDR mode -- HS400 */
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#define SD_DATA_4BIT 0x00040000
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#define IS_SD(x) (x->version & SD_VERSION_SD)
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#define MMC_DATA_READ (1U<<0)
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#define MMC_DATA_WRITE (1U<<1)
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#define MMC_CMD_MANUAL 1//add by sunxi.not sent stop when read/write multi block,and sent stop when sent cmd12
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#define NO_CARD_ERR -16 /* No SD/MMC card inserted */
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#define UNUSABLE_ERR -17 /* Unusable Card */
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#define COMM_ERR -18 /* Communications Error */
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#define TIMEOUT -19
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#define MMC_CMD_GO_IDLE_STATE 0
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#define MMC_CMD_SEND_OP_COND 1
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#define MMC_CMD_ALL_SEND_CID 2
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#define MMC_CMD_SET_RELATIVE_ADDR 3
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#define MMC_CMD_SET_DSR 4
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#define MMC_CMD_SWITCH 6
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#define MMC_CMD_SELECT_CARD 7
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#define MMC_CMD_SEND_EXT_CSD 8
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#define MMC_CMD_SEND_CSD 9
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#define MMC_CMD_SEND_CID 10
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#define MMC_CMD_STOP_TRANSMISSION 12
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#define MMC_CMD_SEND_STATUS 13
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#define MMC_CMD_SET_BLOCKLEN 16
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#define MMC_CMD_READ_SINGLE_BLOCK 17
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#define MMC_CMD_READ_MULTIPLE_BLOCK 18
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#define MMC_CMD_WRITE_SINGLE_BLOCK 24
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#define MMC_CMD_WRITE_MULTIPLE_BLOCK 25
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#define MMC_CMD_ERASE_GROUP_START 35
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#define MMC_CMD_ERASE_GROUP_END 36
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#define MMC_CMD_ERASE 38
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#define MMC_CMD_APP_CMD 55
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#define MMC_CMD_SPI_READ_OCR 58
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#define MMC_CMD_SPI_CRC_ON_OFF 59
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#define SD_CMD_SEND_RELATIVE_ADDR 3
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#define SD_CMD_SWITCH_FUNC 6
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#define SD_CMD_SEND_IF_COND 8
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#define SD_CMD_APP_SET_BUS_WIDTH 6
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#define SD_CMD_ERASE_WR_BLK_START 32
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#define SD_CMD_ERASE_WR_BLK_END 33
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#define SD_CMD_APP_SEND_OP_COND 41
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#define SD_CMD_APP_SEND_SCR 51
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/* SCR definitions in different words */
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#define SD_HIGHSPEED_BUSY 0x00020000
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#define SD_HIGHSPEED_SUPPORTED 0x00020000
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#define MMC_HS_TIMING 0x00000100
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#define MMC_HS_52MHZ 0x2
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#define MMC_DDR_52MHZ 0x4
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#define OCR_BUSY 0x80000000
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#define OCR_HCS 0x40000000
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#define OCR_VOLTAGE_MASK 0x007FFF80
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#define OCR_ACCESS_MODE 0x60000000
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#define SECURE_ERASE 0x80000000
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#define MMC_STATUS_MASK (~0x0206BF7F)
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#define MMC_STATUS_RDY_FOR_DATA (1 << 8)
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#define MMC_STATUS_CURR_STATE (0xf << 9)
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#define MMC_STATUS_ERROR (1 << 19)
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#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
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#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
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#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
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#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
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#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
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#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
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#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
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#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
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#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
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#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
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#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
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#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
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#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
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#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
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#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
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#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
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#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
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#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
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#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte
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addressed by index which are
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1 in value field */
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#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte
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addressed by index, which are
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1 in value field */
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#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */
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#define SD_SWITCH_CHECK 0
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#define SD_SWITCH_SWITCH 1
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/*
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* EXT_CSD fields
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*/
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#define EXT_CSD_PART_CONF 179 /* R/W */
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#define EXT_CSD_BUS_WIDTH 183 /* R/W */
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#define EXT_CSD_HS_TIMING 185 /* R/W */
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#define EXT_CSD_CARD_TYPE 196 /* RO */
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#define EXT_CSD_REV 192 /* RO */
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#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
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/*
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* EXT_CSD field definitions
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*/
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#define EXT_CSD_CMD_SET_NORMAL (1 << 0)
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#define EXT_CSD_CMD_SET_SECURE (1 << 1)
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#define EXT_CSD_CMD_SET_CPSECURE (1 << 2)
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//#define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */
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//#define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */
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/* -- EXT_CSD[196] DEVICE_TYPE */
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#define EXT_CSD_CARD_TYPE_HS_26 (1<<0) /* Card can run at 26MHz */
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#define EXT_CSD_CARD_TYPE_HS_52 (1<<1) /* Card can run at 52MHz */
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#define EXT_CSD_CARD_TYPE_HS (EXT_CSD_CARD_TYPE_HS_26 | EXT_CSD_CARD_TYPE_HS_52)
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#define EXT_CSD_CARD_TYPE_DDR_1_8V (1<<2) /* Card can run at 52MHz */ /* DDR mode @1.8V or 3V I/O */
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#define EXT_CSD_CARD_TYPE_DDR_1_2V (1<<3) /* Card can run at 52MHz */ /* DDR mode @1.2V I/O */
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#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V | EXT_CSD_CARD_TYPE_DDR_1_2V)
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#define EXT_CSD_CARD_TYPE_HS200_1_8V (1<<4) /* Card can run at 200MHz */
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#define EXT_CSD_CARD_TYPE_HS200_1_2V (1<<5) /* Card can run at 200MHz *//* SDR mode @1.2V I/O */
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#define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | EXT_CSD_CARD_TYPE_HS200_1_2V)
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#define EXT_CSD_CARD_TYPE_HS400_1_8V (1<<6) /* Card can run at 200MHz DDR, 1.8V */
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#define EXT_CSD_CARD_TYPE_HS400_1_2V (1<<7) /* Card can run at 200MHz DDR, 1.2V */
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#define EXT_CSD_CARD_TYPE_HS400 (EXT_CSD_CARD_TYPE_HS400_1_8V | EXT_CSD_CARD_TYPE_HS400_1_2V)
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/* -- EXT_CSD[183] BUS_WIDTH */
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#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
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#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
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#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
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#define EXT_CSD_BUS_DDR_4 5 /* Card is in 4 bit ddr mode */
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#define EXT_CSD_BUS_DDR_8 6 /* Card is in 8 bit ddr mode */
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/* -- EXT_CSD[185] HS_TIMING */
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#define EXT_CSD_TIMING_BC 0 /* Backwards compatibility */
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#define EXT_CSD_TIMING_HS 1 /* High speed */
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#define EXT_CSD_TIMING_HS200 2 /* HS200 */
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#define EXT_CSD_TIMING_HS400 3 /* HS400 */
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#define R1_ILLEGAL_COMMAND (1 << 22)
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#define R1_APP_CMD (1 << 5)
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#define MMC_RSP_PRESENT (1 << 0)
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#define MMC_RSP_136 (1 << 1) /* 136 bit response */
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#define MMC_RSP_CRC (1 << 2) /* expect valid crc */
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#define MMC_RSP_BUSY (1 << 3) /* card may send busy */
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#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
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#define MMC_RSP_NONE (0)
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#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
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#define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
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MMC_RSP_BUSY)
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#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
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#define MMC_RSP_R3 (MMC_RSP_PRESENT)
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#define MMC_RSP_R4 (MMC_RSP_PRESENT)
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#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
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#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
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#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
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#define MMCPART_NOAVAILABLE (0xff)
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#define PART_ACCESS_MASK (0x7)
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#define PART_SUPPORT (0x1)
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/*
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struct mmc_cid {
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unsigned long psn;
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unsigned short oid;
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unsigned char mid;
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unsigned char prv;
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unsigned char mdt;
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char pnm[7];
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};
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*/
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/*
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* WARNING!
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*
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* This structure is used by atmel_mci.c only.
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* It works for the AVR32 architecture but NOT
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* for ARM/AT91 architectures.
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* Its use is highly depreciated.
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* After the atmel_mci.c driver for AVR32 has
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* been replaced this structure will be removed.
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*/
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/*
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struct mmc_csd
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{
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u8 csd_structure:2,
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spec_vers:4,
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rsvd1:2;
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u8 taac;
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u8 nsac;
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u8 tran_speed;
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u16 ccc:12,
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read_bl_len:4;
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u64 read_bl_partial:1,
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write_blk_misalign:1,
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read_blk_misalign:1,
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dsr_imp:1,
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rsvd2:2,
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c_size:12,
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vdd_r_curr_min:3,
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vdd_r_curr_max:3,
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vdd_w_curr_min:3,
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vdd_w_curr_max:3,
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c_size_mult:3,
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sector_size:5,
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erase_grp_size:5,
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wp_grp_size:5,
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wp_grp_enable:1,
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default_ecc:2,
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r2w_factor:3,
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write_bl_len:4,
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write_bl_partial:1,
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rsvd3:5;
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u8 file_format_grp:1,
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copy:1,
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perm_write_protect:1,
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tmp_write_protect:1,
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file_format:2,
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ecc:2;
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u8 crc:7;
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u8 one:1;
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};
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*/
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#if 0
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struct tuning_sdly{
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//u8 sdly_400k;
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u8 sdly_25M;
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u8 sdly_50M;
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u8 sdly_100M;
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u8 sdly_200M;
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};//size can not over 256 now
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#else
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/*
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-- speed mode --
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sm0: DS26_SDR12
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sm1: HSSDR52_SDR25
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sm2: HSDDR52_DDR50
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sm3: HS200_SDR104
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sm4: HS400
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-- frequency point --
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f0: CLK_400K
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f1: CLK_25M
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f2: CLK_50M
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f3: CLK_100M
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f4: CLK_150M
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f5: CLK_200M
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*/
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struct tune_sdly {
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/*
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u32 tm4_sm0_f3210;
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u32 tm4_sm0_f7654;
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u32 tm4_sm1_f3210;
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u32 tm4_sm1_f7654;
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u32 tm4_sm2_f3210;
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u32 tm4_sm2_f7654;
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u32 tm4_sm3_f3210;
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u32 tm4_sm3_f7654;
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u32 tm4_sm4_f3210;
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u32 tm4_sm4_f7654;
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*/
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u32 tm4_smx_fx[12];
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};
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struct boot_mmc_cfg {
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u8 boot0_para;
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u8 boot_odly_50M;
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u8 boot_sdly_50M;
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u8 boot_odly_50M_ddr;
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u8 boot_sdly_50M_ddr;
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u8 boot_hs_f_max;
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u8 res[2];
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};
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#define SDMMC_PRIV_INFO_ADDR_OFFSET (128)
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struct boot_sdmmc_private_info_t {
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struct tune_sdly tune_sdly;
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struct boot_mmc_cfg boot_mmc_cfg;
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#define CARD_TYPE_SD 0x8000001
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#define CARD_TYPE_MMC 0x8000000
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#define CARD_TYPE_NULL 0xffffffff
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u32 card_type; /*0xffffffff: invalid; 0x8000000: mmc card; 0x8000001: sd card*/
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#define EXT_PARA0_ID (0x55000000)
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#define EXT_PARA0_TUNING_SUCCESS_FLAG (1U<<0)
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u32 ext_para0;
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/*GPIO 1.8V bias setting*/
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#define EXT_PARA1_1V8_GPIO_BIAS 0x1
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u32 ext_para1;
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/* ext_para2/3 reseved for future */
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u32 ext_para2;
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u32 ext_para3;
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};
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#endif
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struct sunxi_sdmmc_parameter_region_header {
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u8 name[16]; //sdmmc_arg
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#define REGION_VERSION 0x0001
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u32 version; // describe the region version
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#define SDMMC_PARAMETER_MAGIC 0x6D6D6361 // mmca
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u32 magic;
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u32 add_sum;
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u32 length;
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u8 reserved[16];
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};
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struct sunxi_sdmmc_parameter_region {
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#define SUNXI_SDMMC_PARAMETER_REGION_LBA_START 24504
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#define SUNXI_SDMMC_PARAMETER_REGION_SIZE_BYTE 512
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struct sunxi_sdmmc_parameter_region_header header;
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struct boot_sdmmc_private_info_t info;
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};
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struct mmc {
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char name[32];
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void *priv;
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unsigned voltages;
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unsigned version;
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unsigned has_init;
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unsigned control_num;
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unsigned f_min;
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unsigned f_max;
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unsigned f_max_ddr;
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int high_capacity;
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unsigned bus_width;
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unsigned clock;
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unsigned card_caps;
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unsigned host_caps;
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unsigned ocr;
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unsigned scr[2];
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unsigned csd[4];
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unsigned cid[4];
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unsigned rca; //unsigned short rca;
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unsigned part_config; //char part_config;
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unsigned part_num; //char part_num;
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unsigned tran_speed;
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unsigned read_bl_len;
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unsigned write_bl_len;
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unsigned erase_grp_size;
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unsigned long long capacity;
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int (*send_cmd)(struct mmc *mmc,
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struct mmc_cmd *cmd, struct mmc_data *data);
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void (*set_ios)(struct mmc *mmc);
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int (*init)(struct mmc *mmc);
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int (*update_phase)(struct mmc *mmc);
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struct tune_sdly tune_sdly;
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unsigned b_max;
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unsigned lba; /* number of blocks */
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unsigned blksz; /* block size */
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char revision[8+8]; //char revision[8+1]; /* CID: PRV */
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uint speed_mode;
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};
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struct sunxi_mmc {
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volatile u32 gctrl; /* (0x00) SMC Global Control Register */
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volatile u32 clkcr; /* (0x04) SMC Clock Control Register */
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volatile u32 timeout; /* (0x08) SMC Time Out Register */
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volatile u32 width; /* (0x0C) SMC Bus Width Register */
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volatile u32 blksz; /* (0x10) SMC Block Size Register */
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volatile u32 bytecnt; /* (0x14) SMC Byte Count Register */
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volatile u32 cmd; /* (0x18) SMC Command Register */
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volatile u32 arg; /* (0x1C) SMC Argument Register */
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volatile u32 resp0; /* (0x20) SMC Response Register 0 */
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volatile u32 resp1; /* (0x24) SMC Response Register 1 */
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volatile u32 resp2; /* (0x28) SMC Response Register 2 */
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volatile u32 resp3; /* (0x2C) SMC Response Register 3 */
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volatile u32 imask; /* (0x30) SMC Interrupt Mask Register */
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volatile u32 mint; /* (0x34) SMC Masked Interrupt Status Register */
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volatile u32 rint; /* (0x38) SMC Raw Interrupt Status Register */
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volatile u32 status; /* (0x3C) SMC Status Register */
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volatile u32 ftrglevel; /* (0x40) SMC FIFO Threshold Watermark Register */
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volatile u32 funcsel; /* (0x44) SMC Function Select Register */
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volatile u32 cbcr; /* (0x48) SMC CIU Byte Count Register */
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volatile u32 bbcr; /* (0x4C) SMC BIU Byte Count Register */
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volatile u32 dbgc; /* (0x50) SMC Debug Enable Register */
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volatile u32 csdc; /* (0x54) CRC status detect control register*/
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volatile u32 a12a; /* (0x58)Auto command 12 argument*/
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volatile u32 ntsr; /* (0x5c)SMC2 Newtiming Set Register */
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volatile u32 res1[6]; /* (0x54~0x74) */
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volatile u32 hwrst; /* (0x78) SMC eMMC Hardware Reset Register */
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volatile u32 res2; /* (0x7c) */
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volatile u32 dmac; /* (0x80) SMC IDMAC Control Register */
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volatile u32 dlba; /* (0x84) SMC IDMAC Descriptor List Base Address Register */
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volatile u32 idst; /* (0x88) SMC IDMAC Status Register */
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volatile u32 idie; /* (0x8C) SMC IDMAC Interrupt Enable Register */
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volatile u32 chda; /* (0x90) */
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volatile u32 cbda; /* (0x94) */
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volatile u32 res3[26]; /* (0x98~0xff) */
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volatile u32 thldc; /* (0x100) Card Threshold Control Register */
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volatile u32 res4[2]; /* (0x104~0x10b) */
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volatile u32 dsbd; /* (0x10c) eMMC4.5 DDR Start Bit Detection Control */
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volatile u32 res5[12]; /* (0x110~0x13c) */
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volatile u32 drv_dl; /* (0x140) drive delay control register*/
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volatile u32 samp_dl; /* (0x144) sample delay control register*/
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volatile u32 ds_dl; /* (0x148) data strobe delay control register */
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volatile u32 res6[45]; /* (0x110~0x1ff) */
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volatile u32 fifo; /* (0x200) SMC FIFO Access Address */
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};
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#define mmc_host_is_spi(mmc) ((mmc)->host_caps & MMC_MODE_SPI)
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#endif /* _MMC_H_ */
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