142 lines
4.0 KiB
Plaintext
142 lines
4.0 KiB
Plaintext
/{
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clocks {
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compatible = "allwinner,clk-init";
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device_type = "clocks";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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reg = <0x0 0x03001000 0x0 0x1000>, /*cpux space*/
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<0x0 0x07010000 0x0 0x400>, /*cpus space*/
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<0x0 0x07000000 0x0 0x4>;
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clk_pll_periph0: pll_periph0 {
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#clock-cells = <0>;
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compatible = "allwinner,pll-clock";
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assigned-clock-rates = <600000000>;
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lock-mode = "new";
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clock-output-names = "pll_periph0";
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};
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clk_pll_video0x4: pll_video0x4 {
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#clock-cells = <0>;
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compatible = "allwinner,pll-clock";
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lock-mode = "new";
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clock-output-names = "pll_video0x4";
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};
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clk_pll_video1x4: pll_video1x4 {
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#clock-cells = <0>;
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compatible = "allwinner,pll-clock";
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lock-mode = "new";
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clock-output-names = "pll_video1x4";
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};
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clk_pll_video2: pll_video2 {
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#clock-cells = <0>;
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compatible = "allwinner,pll-clock";
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lock-mode = "new";
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assigned-clocks = <&clk_pll_video2>;
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assigned-clock-rates = <336000000>;
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clock-output-names = "pll_video2";
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};
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/* register fixed factor clock*/
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clk_pll_periph0x2: pll_periph0x2 {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-factor-clock";
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clocks = <&clk_pll_periph0>;
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clock-mult = <2>;
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clock-div = <1>;
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clock-output-names = "pll_periph0x2";
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};
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clk_de0: de0 {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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assigned-clock-parents = <&clk_pll_periph0x2>;
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assigned-clock-rates = <300000000>;
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assigned-clocks = <&clk_de0>;
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clock-output-names = "de0";
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};
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clk_de1: de1 {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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assigned-clock-parents = <&clk_pll_periph0x2>;
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assigned-clock-rates = <300000000>;
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assigned-clocks = <&clk_de1>;
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clock-output-names = "de1";
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};
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/* clk_g2d: g2d {
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* #clock-cells = <0>;
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* compatible = "allwinner,periph-clock";
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* clock-output-names = "g2d";
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* assigned-clock-parents = <&clk_pll_periph0x2>;
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* assigned-clock-rates = <300000000>;
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* assigned-clocks = <&clk_g2d>;
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* };
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* */
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clk_ee: ee {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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assigned-clock-parents = <&clk_pll_periph0x2>;
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assigned-clock-rates = <300000000>;
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assigned-clocks = <&clk_ee>;
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clock-output-names = "ee";
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};
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clk_panel: panel {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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assigned-clock-parents = <&clk_pll_video2>;
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assigned-clock-rates = <30000000>;
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assigned-clocks = <&clk_panel>;
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clock-output-names = "panel";
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};
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clk_display_top: display_top {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "display_top";
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};
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clk_dpss_top0: dpss_top0 {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "dpss_top0";
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};
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clk_dpss_top1: dpss_top1 {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "dpss_top1";
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};
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clk_tcon_lcd0: tcon_lcd0 {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "tcon_lcd0";
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assigned-clocks = <&clk_tcon_lcd0>;
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assigned-clock-parents = <&clk_pll_video0x4>;
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};
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clk_tcon_lcd1: tcon_lcd1 {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "tcon_lcd1";
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assigned-clocks = <&clk_tcon_lcd1>;
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assigned-clock-parents = <&clk_pll_video1x4>;
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};
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clk_lvds: lvds {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "lvds";
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};
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clk_lvds1: lvds1 {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "lvds1";
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};
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clk_mipi_host: mipi_host {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "mipi_host";
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assigned-clocks = <&clk_mipi_host>;
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assigned-clock-parents = <&clk_pll_periph0>;
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assigned-clock-rates = <150000000>;
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};
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};
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};
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