374 lines
8.4 KiB
Plaintext
374 lines
8.4 KiB
Plaintext
/*
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* Allwinner Technology CO., Ltd. sun8iw21p1 platform
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*
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* modify base on juno.dts
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*/
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/gpio/gpio.h>
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#include "sun8iw11p1-clk.dtsi"
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/*#include "sun8iw21p1-pinctrl.dtsi"*/
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#include <dt-bindings/thermal/thermal.h>
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/ {
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model = "sun8iw21";
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compatible = "allwinner,a40i", "arm,sun8iw11p1";
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#address-cells = <2>;
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#size-cells = <2>;
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soc: soc@29000000 {
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#address-cells = <2>;
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#size-cells = <2>;
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device_type = "soc";
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power_sply:power_sply@4500000c {
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device_type = "power_sply";
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};
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power_delay:power_delay@4500024 {
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device_type = "power_delay";
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};
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platform:platform@45000004 {
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device_type = "platform";
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};
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target:target@45000008 {
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device_type = "target";
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boot_clock = <900>;
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};
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charger0:charger0@45000010 {
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device_type = "charger0";
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};
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card_boot:card_boot@45000014 {
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device_type = "card_boot";
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logical_start = <40960>;
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/* sprite_gpio0 = <&pio PH 6 1 0xffffffff 0xffffffff 1>; */
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sprite_gpio0 = <&pio 0x7 0x6 0x1 0xffffffff 0xffffffff 0x1>;
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};
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gpio_bias:gpio_bias@45000018 {
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device_type = "gpio_bias";
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};
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sunxi_flashmap:sunxi_flashmap@45000018 {
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device_type = "sunxi_flashmap";
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};
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fastboot_key:fastboot_key@4500001c {
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device_type = "fastboot_key";
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key_max = <42>;
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key_min = <38>;
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};
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recovery_key:recovery_key@45000020 {
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device_type = "recovery_key";
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key_max = <31>;
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key_min = <28>;
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};
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pio: pinctrl@0300b000 {
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compatible = "allwinner,sun8iw11p1-pinctrl";
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device_type = "pio";
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gpio-controller;
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#size-cells = <0>;
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#gpio-cells = <6>;
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/* takes the debounce time in usec as argument */
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input-debounce = <0 0 0 0 0 0 0 0 0>;
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r_pio: pinctrl@07022000 {
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};
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sdc0_pins_a: sdc0@0 {
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};
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sdc0_pins_b: sdc0@1 {
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};
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sdc0_pins_c: sdc0@2 {
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};
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sdc2_pins_a: sdc2@0 {
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};
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sdc2_pins_b: sdc2@1 {
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};
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sdc2_pins_c: sdc2@2 {
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};
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nand0_pins_a: nand0@0 {
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};
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nand0_pins_b: nand0@1 {
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};
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nand0_pins_c: nand0@2 {
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};
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spi0_pins_a: spi0@0 {
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};
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spi0_pins_cs0: spi0@1 {
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};
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spi0_pins_cs1: spi0@2 {
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};
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spi0_pins_c: spi0@3 {
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};
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dsi4lane_pins_a: dsi4lane@0 {
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allwinner,pins = "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD9", "PD10", "PD11";
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allwinner,pname = "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD9", "PD10", "PD11";
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allwinner,function = "dsi4lane";
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allwinner,muxsel = <5>;
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allwinner,drive = <3>;
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allwinner,pull = <0>;
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};
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dsi4lane_pins_b: dsi4lane@1 {
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allwinner,pins = "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD9", "PD10", "PD11";
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allwinner,pname = "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD9", "PD10", "DP11";
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allwinner,function = "dsi4lane_suspend";
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allwinner,muxsel = <7>;
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allwinner,drive = <1>;
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allwinner,pull = <0>;
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};
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rgb18_pins_a: rgb18@0 {
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};
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rgb18_pins_b: rgb18@1 {
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};
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};
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twi0: twi@1c2ac00 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "allwinner,sun8i-twi";
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device_type = "twi0";
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reg = <0x0 0x01c2ac00 0x0 0x400>;
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status = "disabled";
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};
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twi1: twi@1c2b000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "allwinner,sun8i-twi";
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device_type = "twi1";
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reg = <0x0 0x01c2b000 0x0 0x400>;
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status = "disabled";
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};
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twi2: twi@1c2b400 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "allwinner,sun8i-twi";
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device_type = "twi2";
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reg = <0x0 0x01c2b400 0x0 0x400>;
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status = "disabled";
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};
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twi3: twi@1c2b800 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "allwinner,sun8i-twi";
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device_type = "twi3";
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reg = <0x0 0x01c2b800 0x0 0x400>;
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status = "disabled";
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};
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twi4: twi@1c2c000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "allwinner,sun8i-twi";
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device_type = "twi4";
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reg = <0x0 0x1c2c000 0x0 0x400>;
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status = "disabled";
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};
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gmac0: gmac0@01c50000 {
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compatible = "allwinner,sunxi-gmac";
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reg = <0x0 0x01c50000 0x0 0x1000>,
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<0x0 0x01c20164 0x0 0x04>;
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status = "okay";
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};
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emac0: emac0@1c0b000 {
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compatible = "allwinner,sunxi-emac";
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reg = <0x0 0x01c0b000 0x0 0x0c000>;
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status = "okay";
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};
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pwm: pwm@1c23400 {
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#pwm-cells = <0x3>;
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compatible = "allwinner,sunxi-pwm-v101";
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reg = <0x0 0x01c23400 0x0 0x400>;
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pwm-number = <8>;
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pwm-base = <0x0>;
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sunxi-pwms = <&pwm0>, <&pwm1>, <&pwm2>, <&pwm3>, <&pwm4>, <&pwm5>, <&pwm6>, <&pwm7>;
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};
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pwm0: pwm0@1c23410 {
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#pwm-cells = <0x3>;
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compatible = "allwinner,sunxi-pwm0";
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reg = <0x0 0x01c23410 0x0 0x4>;
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reg_base = <0x01c23400>;
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status = "disabled";
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};
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pwm1: pwm1@1c23411 {
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#pwm-cells = <0x3>;
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compatible = "allwinner,sunxi-pwm1";
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reg = <0x0 0x01c23411 0x0 0x4>;
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reg_base = <0x01c23400>;
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status = "disabled";
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};
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pwm2: pwm2@1c23412 {
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#pwm-cells = <0x3>;
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compatible = "allwinner,sunxi-pwm2";
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reg = <0x0 0x01c23412 0x0 0x4>;
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reg_base = <0x01c23400>;
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status = "disabled";
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};
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pwm3: pwm3@1c23413 {
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#pwm-cells = <0x3>;
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compatible = "allwinner,sunxi-pwm3";
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reg = <0x0 0x01c23413 0x0 0x4>;
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reg_base = <0x01c23400>;
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status = "disabled";
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};
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pwm4: pwm4@1c23414 {
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#pwm-cells = <0x3>;
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compatible = "allwinner,sunxi-pwm4";
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reg = <0x0 0x01c23414 0x0 0x4>;
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reg_base = <0x01c23400>;
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status = "disabled";
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};
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pwm5: pwm5@1c23415 {
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#pwm-cells = <0x3>;
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compatible = "allwinner,sunxi-pwm5";
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reg = <0x0 0x01c23415 0x0 0x4>;
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reg_base = <0x01c23400>;
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status = "disabled";
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};
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pwm6: pwm6@1c23416 {
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#pwm-cells = <0x3>;
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compatible = "allwinner,sunxi-pwm6";
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reg = <0x0 0x01c23416 0x0 0x4>;
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reg_base = <0x01c23400>;
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status = "disabled";
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};
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pwm7: pwm7@1c23417 {
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#pwm-cells = <0x3>;
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compatible = "allwinner,sunxi-pwm7";
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reg = <0x0 0x01c23417 0x0 0x4>;
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reg_base = <0x01c23400>;
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status = "disabled";
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};
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card0_boot_para:card0_boot_para@2 {
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device_type = "card0_boot_para";
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};
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card2_boot_para:card2_boot_para@3 {
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device_type = "card2_boot_para";
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};
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nand0:nand0@04011000 {
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device_type = "nand0";
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};
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spi0: spi@4025000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "allwinner,sun20i-spi";
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device_type = "spi0";
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reg = <0x0 0x04025000 0x0 0x300>;
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//interrupts-extended = <&plic0 31 IRQ_TYPE_LEVEL_HIGH>;
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//clocks = <&ccu CLK_PLL_PERIPH0>, <&ccu CLK_SPI0>, <&ccu CLK_BUS_SPI0>;
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//clock-names = "pll", "mod", "bus";
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//resets = <&ccu RST_BUS_SPI0>;
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};
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spif: spif@4f00000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "allwinner,sun8i-spif";
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device_type = "spif";
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reg = <0x0 0x04f00000 0x0 0x1000>;
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//interrupts-extended = <&plic0 19 IRQ_TYPE_LEVEL_HIGH>;
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//clocks = <&ccu CLK_PLL_PERIPH0>, <&ccu CLK_SPIF>, <&ccu CLK_BUS_SPIF>;
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//clock-names = "pll", "mod", "bus";
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//resets = <&ccu RST_BUS_SPIF>;
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};
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disp: disp@01000000 {
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compatible = "allwinner,sun50i-disp";
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reg = <0x0 0x01000000 0x0 0x00300000>,/*de*/
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<0x0 0x01c70000 0x0 0xfff>,/*tcon top*/
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<0x0 0x01c71000 0x0 0xfff>,/*tcon0*/
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<0x0 0x01c72000 0x0 0xfff>,/*tcon1*/
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<0x0 0x01c73000 0x0 0xfff>,/*tcon2*/
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<0x0 0x01c74000 0x0 0xfff>,/*tcon3*/
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<0x0 0x01ca0000 0x0 0x10fc>;/*dsi*/
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interrupts = <GIC_SPI 44 0x0104>, <GIC_SPI 45 0x0104>,
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<GIC_SPI 51 0x0104>, <GIC_SPI 52 0x0104>,
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<GIC_SPI 57 0x0104>;/* for dsi */
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clocks = <&clk_de>,<&clk_tcon_top>,
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<&clk_tcon0>,<&clk_tcon1>,
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<&clk_tcon_tv0>,<&clk_tcon_tv1>,<&clk_lvds>,<&clk_mipidsi>;
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boot_disp = <0>;
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fb_base = <0>;
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status = "okay";
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};
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lcd0: lcd0@01c0c000 {
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compatible = "allwinner,sunxi-lcd0";
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pinctrl-names = "active","sleep";
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status = "okay";
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};
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lcd1: lcd1@01c0c001 {
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compatible = "allwinner,sunxi-lcd1";
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pinctrl-names = "active","sleep";
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status = "okay";
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};
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clk_test: clk_test@0x12345 {
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// clocks = <&clk_de>,
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// <&clk_dpss_top>,
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// <&clk_tcon_lcd>,
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// <&clk_mipi_dsi>;
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status = "okay";
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};
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};
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gic: interrupt-controller@3020000 {
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compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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device_type = "gic";
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interrupt-controller;
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reg = <0x0 0x03021000 0 0x1000>, /* GIC Dist */
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<0x0 0x03022000 0 0x2000>, /* GIC CPU */
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<0x0 0x03024000 0 0x2000>, /* GIC VCPU Control */
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<0x0 0x03026000 0 0x2000>; /* GIC VCPU */
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interrupts = <GIC_PPI 9 0xf04>; /* GIC Maintenence IRQ */
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interrupt-parent = <&gic>;
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};
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aliases:aliases@45100000 {
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};
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};
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#include ".board-uboot.dts"
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