1341 lines
32 KiB
Plaintext
1341 lines
32 KiB
Plaintext
/*
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* Allwinner Technology CO., Ltd. sun8iw18p1 soc board.
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*
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* soc board support.
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*/
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/gpio/gpio.h>
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/*#include "sun8iw18p1-clk.dtsi"*/
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/*#include "sun8iw18p1-pinctrl.dtsi"*/
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/ {
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model = "sun8iw18";
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compatible = "allwinner,sun8iw18p1";
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interrupt-parent = <&wakeupgen>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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serial0 = &uart0;
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twi0 = &twi0;
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twi1 = &twi1;
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spi0 = &spi0;
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spi1 = &spi1;
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spinand = &spinand;
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nand0_para = &spinand;
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ledc = &ledc;
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nand0 =&nand0;
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pwm = &pwm;
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pwm0 = &pwm0;
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pwm1 = &pwm1;
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pwm2 = &pwm2;
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pwm3 = &pwm3;
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pwm4 = &pwm4;
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pwm5 = &pwm5;
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pwm6 = &pwm6;
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pwm7 = &pwm7;
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boot_disp = &boot_disp;
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};
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gic: interrupt-controller@03020000 {
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compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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device_type = "gic";
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interrupt-controller;
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reg = <0x0 0x03021000 0 0x1000>, /* GIC Dist */
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<0x0 0x03022000 0 0x2000>, /* GIC CPU */
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<0x0 0x03024000 0 0x2000>, /* GIC VCPU Control */
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<0x0 0x03026000 0 0x2000>; /* GIC VCPU */
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interrupts = <GIC_PPI 9 0xf04>; /* GIC Maintenence IRQ */
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interrupt-parent = <&gic>;
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};
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wakeupgen: interrupt-controller@0 {
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compatible = "allwinner,sunxi-wakeupgen";
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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};
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soc: soc@03000000 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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device_type = "soc";
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platform {
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device_type = "platform";
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eraseflag = <0x1>;
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next_work = <0x3>;
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};
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target {
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device_type = "target";
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boot_clock = <1008>;
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storage_type = <0xffffffff>;
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burn_key = <0x0>;
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auto_fel = <0x0>;
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};
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pio: pinctrl@0300b000 {
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compatible = "allwinner,sun8iw18p1-pinctrl";
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reg = <0x0 0x0300b000 0x0 0x400>;
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interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
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device_type = "pio";
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/*clocks = <&clk_pio>;*/
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <3>;
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#size-cells = <0>;
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#gpio-cells = <6>;
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vdevice_pins_a: vdevice@0 {
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allwinner,pins = "PE0", "PE1";
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allwinner,function = "vdevice";
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allwinner,muxsel = <5>;
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allwinner,drive = <1>;
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allwinner,pull = <1>;
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};
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uart0_pins_a: uart0@0 {
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allwinner,pins = "PH0", "PH1";
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allwinner,pname = "uart0_tx", "uart0_rx";
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allwinner,function = "uart0";
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allwinner,muxsel = <3>;
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allwinner,drive = <1>;
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allwinner,pull = <1>;
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};
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uart0_pins_b: uart0@1 {
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allwinner,pins = "PH0", "PH1";
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allwinner,function = "io_disabled";
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allwinner,muxsel = <7>;
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allwinner,drive = <1>;
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allwinner,pull = <0>;
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};
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uart1_pins_a: uart1@0 {
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allwinner,pins = "PG6", "PG7", "PG8", "PG9";
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allwinner,pname = "uart1_tx", "uart1_rx",
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"uart1_rts", "uart1_cts";
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allwinner,function = "uart1";
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allwinner,muxsel = <2>;
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allwinner,drive = <1>;
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allwinner,pull = <1>;
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};
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uart1_pins_b: uart1@1 {
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allwinner,pins = "PG6", "PG7", "PG8", "PG9";
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allwinner,function = "io_disabled";
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allwinner,muxsel = <7>;
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allwinner,drive = <1>;
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allwinner,pull = <0>;
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};
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uart2_pins_a: uart2@0 {
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allwinner,pins = "PB0", "PB1", "PB2", "PB3";
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allwinner,pname = "uart2_tx", "uart2_rx",
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"uart2_rts", "uart2_cts";
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allwinner,function = "uart2";
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allwinner,muxsel = <2>;
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allwinner,drive = <1>;
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allwinner,pull = <1>;
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};
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uart2_pins_b: uart2@1 {
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allwinner,pins = "PB0", "PB1", "PB2", "PB3";
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allwinner,function = "io_disabled";
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allwinner,muxsel = <7>;
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allwinner,drive = <1>;
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allwinner,pull = <0>;
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};
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uart3_pins_a: uart3@0 {
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allwinner,pins = "PH4", "PH5", "PH6", "PH7";
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allwinner,pname = "uart3_tx", "uart3_rx",
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"uart3_rts", "uart3_cts";
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allwinner,function = "uart3";
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allwinner,muxsel = <2>;
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allwinner,drive = <1>;
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allwinner,pull = <1>;
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};
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uart3_pins_b: uart3@1 {
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allwinner,pins = "PH4", "PH5", "PH6", "PH7";
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allwinner,function = "io_disabled";
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allwinner,muxsel = <7>;
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allwinner,drive = <1>;
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allwinner,pull = <0>;
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};
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twi0_pins_a: twi0@0 {
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allwinner,pins = "PH0", "PH1";
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allwinner,pname = "twi0_scl", "twi0_sda";
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allwinner,function = "twi0";
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allwinner,muxsel = <2>;
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allwinner,drive = <1>;
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allwinner,pull = <0>;
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};
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twi0_pins_b: twi0@1 {
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allwinner,pins = "PH0", "PH1";
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allwinner,function = "io_disabled";
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allwinner,muxsel = <7>;
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allwinner,drive = <1>;
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allwinner,pull = <0>;
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};
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twi1_pins_a: twi1@0 {
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allwinner,pins = "PB8", "PB9";
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allwinner,pname = "twi1_scl", "twi1_sda";
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allwinner,function = "twi1";
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allwinner,muxsel = <4>;
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allwinner,drive = <1>;
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allwinner,pull = <0>;
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};
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twi1_pins_b: twi1@1 {
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allwinner,pins = "PB8", "PB9";
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allwinner,function = "io_disabled";
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allwinner,muxsel = <7>;
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allwinner,drive = <1>;
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allwinner,pull = <0>;
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};
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spi0_pins_a: spi0@0 {
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allwinner,pins = "PC0", "PC2", "PC4", "PC16",
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"PC15";
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allwinner,pname = "spi0_sclk", "spi0_mosi",
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"spi0_miso", "spi0_hold",
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"spi0_wp";
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allwinner,function = "spi0";
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allwinner,muxsel = <4>;
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allwinner,drive = <1>;
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allwinner,pull = <0>;
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};
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spi0_pins_b: spi0@1 {
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allwinner,pins = "PC3";
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allwinner,pname = "spi0_cs0";
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allwinner,function = "spi0";
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allwinner,muxsel = <4>;
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allwinner,drive = <1>;
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allwinner,pull = <1>; // only CS should be pulled up
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};
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spi0_pins_c: spi0@2 {
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allwinner,pins = "PC0", "PC2", "PC3", "PC4",
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"PC15", "PC16";
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allwinner,function = "io_disabled";
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allwinner,muxsel = <7>;
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allwinner,drive = <1>;
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allwinner,pull = <0>;
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};
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spi1_pins_a: spi1@0 {
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allwinner,pins = "PH5", "PH6", "PH7";
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allwinner,pname = "spi1_sclk", "spi1_mosi",
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"spi1_miso";
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allwinner,function = "spi1";
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allwinner,muxsel = <3>;
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allwinner,drive = <1>;
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allwinner,pull = <0>;
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};
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spi1_pins_b: spi1@1 {
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allwinner,pins = "PH4";
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allwinner,pname = "spi1_cs0";
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allwinner,function = "spi1";
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allwinner,muxsel = <3>;
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allwinner,drive = <1>;
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allwinner,pull = <1>; // only CS should be pulled up
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};
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spi1_pins_c: spi1@2 {
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allwinner,pins = "PH4", "PH5", "PH6", "PH7";
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allwinner,function = "io_disabled";
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allwinner,muxsel = <7>;
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allwinner,drive = <1>;
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allwinner,pull = <0>;
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};
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nand0_pins_a: nand0@0 {
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allwinner,pins = "PC0", "PC1", "PC2", "PC5",
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"PC16", "PC15", "PC14", "PC13",
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"PC11", "PC10", "PC9", "PC8",
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"PC12";
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allwinner,pname= "nand0_we", "nand0_ale","nand0_cle", "nand0_nre",
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"nand0_d0", "nand0_d1", "nand0_d2", "nand0_d3",
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"nand0_d4", "nand0_d5", "nand0_d6", "nand0_d7",
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"nand0_ndqs";
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allwinner,function = "nand0";
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allwinner,muxsel = <2>;
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allwinner,drive = <1>;
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allwinner,pull = <0>;
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};
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nand0_pins_b: nand0@1 {
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allwinner,pins = "PC4", "PC6", "PC3", "PC7";
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allwinner,pname= "nand0_ce0", "nand0_rb0", "nand0_ce1", "nand0_rb1";
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allwinner,function = "nand0";
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allwinner,muxsel = <2>;
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allwinner,drive = <1>;
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allwinner,pull = <1>;// only RB&CE should be pulled up
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};
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nand0_pins_c: nand0@2 {
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allwinner,pins = "PC0", "PC1", "PC2", "PC3",
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"PC4", "PC5", "PC6", "PC7",
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"PC8", "PC9", "PC10", "PC11",
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"PC12", "PC13", "PC14", "PC15",
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"PC16";
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allwinner,function = "io_disabled";
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allwinner,muxsel = <7>;
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allwinner,drive = <1>;
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allwinner,pull = <0>;
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};
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ledc_pins_a: ledc@0 {
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allwinner,pins = "PB0";
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allwinner,function = "ledc";
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allwinner,muxsel = <5>;
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allwinner,drive = <1>;
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allwinner,pull = <1>;
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};
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ledc_pins_b: ledc@1 {
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allwinner,pins = "PB0";
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allwinner,function = "io_disabled";
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allwinner,muxsel = <7>;
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allwinner,drive = <1>;
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allwinner,pull = <0>;
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};
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pwm0_pins_a: pwm0@0 {
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allwinner,pins = "PB0";
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allwinner,function = "pwm0";
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allwinner,muxsel = <3>;
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allwinner,drive = <1>;
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allwinner,pull = <1>;
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};
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pwm0_pins_b: pwm0@1 {
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allwinner,pins = "PB0";
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allwinner,function = "pwm0";
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allwinner,muxsel = <7>;
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allwinner,drive = <1>;
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allwinner,pull = <1>;
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};
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pwm1_pins_a: pwm1@0 {
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allwinner,pins = "PB1";
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allwinner,function = "pwm1";
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allwinner,muxsel = <3>;
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allwinner,drive = <1>;
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allwinner,pull = <1>;
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};
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pwm1_pins_b: pwm1@1 {
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allwinner,pins = "PB1";
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allwinner,function = "pwm1";
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allwinner,muxsel = <7>;
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allwinner,drive = <1>;
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allwinner,pull = <1>;
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};
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pwm2_pins_a: pwm2@0 {
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allwinner,pins = "PB2";
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allwinner,function = "pwm2";
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allwinner,muxsel = <3>;
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allwinner,drive = <1>;
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allwinner,pull = <1>;
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};
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pwm2_pins_b: pwm2@1 {
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allwinner,pins = "PB2";
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allwinner,function = "pwm2";
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allwinner,muxsel = <7>;
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allwinner,drive = <1>;
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allwinner,pull = <1>;
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};
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pwm3_pins_a: pwm3@0 {
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allwinner,pins = "PB3";
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allwinner,function = "pwm3";
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allwinner,muxsel = <3>;
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allwinner,drive = <1>;
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allwinner,pull = <1>;
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};
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pwm3_pins_b: pwm3@1 {
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allwinner,pins = "PB3";
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allwinner,function = "pwm3";
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allwinner,muxsel = <7>;
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allwinner,drive = <1>;
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allwinner,pull = <1>;
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};
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pwm4_pins_a: pwm4@0 {
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allwinner,pins = "PB4";
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allwinner,function = "pwm4";
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allwinner,muxsel = <3>;
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allwinner,drive = <1>;
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allwinner,pull = <1>;
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};
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pwm4_pins_b: pwm4@1 {
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allwinner,pins = "PB4";
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allwinner,function = "pwm4";
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allwinner,muxsel = <7>;
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allwinner,drive = <1>;
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allwinner,pull = <1>;
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};
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pwm5_pins_a: pwm5@0 {
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allwinner,pins = "PB5";
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allwinner,function = "pwm5";
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allwinner,muxsel = <3>;
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allwinner,drive = <1>;
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allwinner,pull = <1>;
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};
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pwm5_pins_b: pwm5@1 {
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allwinner,pins = "PB5";
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allwinner,function = "pwm5";
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allwinner,muxsel = <7>;
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allwinner,drive = <1>;
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allwinner,pull = <1>;
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};
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pwm6_pins_a: pwm6@0 {
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allwinner,pins = "PB6";
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allwinner,function = "pwm6";
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allwinner,muxsel = <3>;
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allwinner,drive = <1>;
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allwinner,pull = <1>;
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};
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pwm6_pins_b: pwm6@1 {
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allwinner,pins = "PB6";
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allwinner,function = "pwm6";
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allwinner,muxsel = <7>;
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allwinner,drive = <1>;
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allwinner,pull = <1>;
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};
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pwm7_pins_a: pwm7@0 {
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allwinner,pins = "PB7";
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allwinner,function = "pwm7";
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allwinner,muxsel = <3>;
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allwinner,drive = <1>;
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allwinner,pull = <1>;
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};
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pwm7_pins_b: pwm7@1 {
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allwinner,pins = "PB7";
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allwinner,function = "pwm7";
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allwinner,muxsel = <7>;
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allwinner,drive = <1>;
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allwinner,pull = <1>;
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};
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}; /*end pio*/
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uart0: uart@05000000 {
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compatible = "allwinner,sun8i-uart";
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device_type = "uart0";
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reg = <0x0 0x05000000 0x0 0x400>;
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
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/*clocks = <&clk_uart0>;*/
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&uart0_pins_a>;
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pinctrl-1 = <&uart0_pins_b>;
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uart0_port = <0>;
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uart0_type = <2>;
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status = "okay";
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};
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twi0: twi@0x05002000{
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "allwinner,sun8i-twi";
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device_type = "twi0";
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reg = <0x0 0x05002000 0x0 0x400>;
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interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
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/*clocks = <&clk_twi0>;*/
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clock-frequency = <400000>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&twi0_pins_a>;
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pinctrl-1 = <&twi0_pins_b>;
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status = "disabled";
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};
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twi1: twi@0x05002400{
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "allwinner,sun8i-twi";
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device_type = "twi1";
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reg = <0x0 0x05002400 0x0 0x400>;
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|
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
|
/*clocks = <&clk_twi1>;*/
|
|
clock-frequency = <100000>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&twi1_pins_a>;
|
|
pinctrl-1 = <&twi1_pins_b>;
|
|
status = "disabled";
|
|
};
|
|
|
|
|
|
spi0: spi@05010000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "allwinner,sun8i-spi";
|
|
device_type = "spi0";
|
|
reg = <0x0 0x05010000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
|
/*clocks = <&clk_pll_periph0>, <&clk_spi0>;*/
|
|
clock-frequency = <100000000>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&spi0_pins_a &spi0_pins_b>;
|
|
pinctrl-1 = <&spi0_pins_c>;
|
|
spi0_cs_number = <2>;
|
|
spi0_cs_bitmap = <3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spinand: spinand@05010000 {
|
|
compatible = "allwinner,sunxi-spinand";
|
|
device_type = "spinand";
|
|
reg = <0x0 0x05010000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
|
/*clocks = <&clk_pll_periph0>, <&clk_spi0>;*/
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&spi0_pins_a &spi0_pins_b>;
|
|
pinctrl-1 = <&spi0_pins_c>;
|
|
nand0_regulator1 = "vcc-nand";
|
|
nand0_regulator2 = "none";
|
|
nand0_cache_level = <0x55aaaa55>;
|
|
nand0_flush_cache_num = <0x55aaaa55>;
|
|
nand0_capacity_level = <0x55aaaa55>;
|
|
nand0_id_number_ctl = <0x55aaaa55>;
|
|
nand0_print_level = <0x55aaaa55>;
|
|
nand0_p0 = <0x55aaaa55>;
|
|
nand0_p1 = <0x55aaaa55>;
|
|
nand0_p2 = <0x55aaaa55>;
|
|
nand0_p3 = <0x55aaaa55>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi1: spi@05011000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "allwinner,sun8i-spi";
|
|
device_type = "spi1";
|
|
reg = <0x0 0x05011000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
|
/*clocks = <&clk_pll_periph0>, <&clk_spi1>;*/
|
|
clock-frequency = <100000000>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&spi1_pins_a &spi1_pins_b>;
|
|
pinctrl-1 = <&spi1_pins_c>;
|
|
spi1_cs_number = <1>;
|
|
spi1_cs_bitmap = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
|
|
pwm: pwm@0300a000 {
|
|
compatible = "allwinner,sunxi-pwm";
|
|
reg = <0x0 0x0300a000 0x0 0x3ff>;
|
|
/*clocks = <&clk_pwm>;*/
|
|
pwm-number = <8>;
|
|
pwm-base = <0x0>;
|
|
pwms = <&pwm0>, <&pwm1>, <&pwm2>, <&pwm3>, <&pwm4>,
|
|
<&pwm5>, <&pwm6>, <&pwm7>;
|
|
};
|
|
pwm0: pwm0@0300a000 {
|
|
compatible = "allwinner,sunxi-pwm0";
|
|
pinctrl-names = "active", "sleep";
|
|
pinctrl-0 = <&pwm0_pins_a>;
|
|
pinctrl-1 = <&pwm0_pins_b>;
|
|
reg_base = <0x0300a000>;
|
|
reg_peci_offset = <0x00>;
|
|
reg_peci_shift = <0x00>;
|
|
reg_peci_width = <0x01>;
|
|
|
|
reg_pis_offset = <0x04>;
|
|
reg_pis_shift = <0x00>;
|
|
reg_pis_width = <0x01>;
|
|
|
|
reg_crie_offset = <0x10>;
|
|
reg_crie_shift = <0x00>;
|
|
reg_crie_width = <0x01>;
|
|
|
|
reg_cfie_offset = <0x10>;
|
|
reg_cfie_shift = <0x01>;
|
|
reg_cfie_width = <0x01>;
|
|
|
|
reg_cris_offset = <0x14>;
|
|
reg_cris_shift = <0x00>;
|
|
reg_cris_width = <0x01>;
|
|
|
|
reg_cfis_offset = <0x14>;
|
|
reg_cfis_shift = <0x01>;
|
|
reg_cfis_width = <0x01>;
|
|
|
|
reg_clk_src_offset = <0x20>;
|
|
reg_clk_src_shift = <0x07>;
|
|
reg_clk_src_width = <0x02>;
|
|
|
|
reg_bypass_offset = <0x20>;
|
|
reg_bypass_shift = <0x05>;
|
|
reg_bypass_width = <0x01>;
|
|
|
|
reg_clk_gating_offset = <0x20>;
|
|
reg_clk_gating_shift = <0x04>;
|
|
reg_clk_gating_width = <0x01>;
|
|
|
|
reg_clk_div_m_offset = <0x20>;
|
|
reg_clk_div_m_shift = <0x00>;
|
|
reg_clk_div_m_width = <0x04>;
|
|
|
|
reg_pdzintv_offset = <0x30>;
|
|
reg_pdzintv_shift = <0x08>;
|
|
reg_pdzintv_width = <0x08>;
|
|
|
|
reg_dz_en_offset = <0x30>;
|
|
reg_dz_en_shift = <0x00>;
|
|
reg_dz_en_width = <0x01>;
|
|
|
|
reg_enable_offset = <0x40>;
|
|
reg_enable_shift = <0x00>;
|
|
reg_enable_width = <0x01>;
|
|
|
|
reg_cap_en_offset = <0x44>;
|
|
reg_cap_en_shift = <0x00>;
|
|
reg_cap_en_width = <0x01>;
|
|
|
|
reg_period_rdy_offset = <0x60>;
|
|
reg_period_rdy_shift = <0x0b>;
|
|
reg_period_rdy_width = <0x01>;
|
|
|
|
reg_pul_start_offset = <0x60>;
|
|
reg_pul_start_shift = <0x0a>;
|
|
reg_pul_start_width = <0x01>;
|
|
|
|
reg_mode_offset = <0x60>;
|
|
reg_mode_shift = <0x09>;
|
|
reg_mode_width = <0x01>;
|
|
|
|
reg_act_sta_offset = <0x60>;
|
|
reg_act_sta_shift = <0x08>;
|
|
reg_act_sta_width = <0x01>;
|
|
|
|
reg_prescal_offset = <0x60>;
|
|
reg_prescal_shift = <0x00>;
|
|
reg_prescal_width = <0x08>;
|
|
|
|
reg_entire_offset = <0x64>;
|
|
reg_entire_shift = <0x10>;
|
|
reg_entire_width = <0x10>;
|
|
|
|
reg_active_offset = <0x64>;
|
|
reg_active_shift = <0x00>;
|
|
reg_active_width = <0x10>;
|
|
|
|
};
|
|
|
|
pwm1: pwm1@0300a000 {
|
|
compatible = "allwinner,sunxi-pwm1";
|
|
pinctrl-names = "active", "sleep";
|
|
pinctrl-0 = <&pwm1_pins_a>;
|
|
pinctrl-1 = <&pwm1_pins_b>;
|
|
reg_base = <0x0300a000>;
|
|
reg_peci_offset = <0x00>;
|
|
reg_peci_shift = <0x01>;
|
|
reg_peci_width = <0x01>;
|
|
|
|
reg_pis_offset = <0x04>;
|
|
reg_pis_shift = <0x01>;
|
|
reg_pis_width = <0x01>;
|
|
|
|
reg_crie_offset = <0x10>;
|
|
reg_crie_shift = <0x02>;
|
|
reg_crie_width = <0x01>;
|
|
|
|
reg_cfie_offset = <0x10>;
|
|
reg_cfie_shift = <0x03>;
|
|
reg_cfie_width = <0x01>;
|
|
|
|
reg_cris_offset = <0x14>;
|
|
reg_cris_shift = <0x02>;
|
|
reg_cris_width = <0x01>;
|
|
|
|
reg_cfis_offset = <0x14>;
|
|
reg_cfis_shift = <0x03>;
|
|
reg_cfis_width = <0x01>;
|
|
|
|
reg_clk_src_offset = <0x20>;
|
|
reg_clk_src_shift = <0x07>;
|
|
reg_clk_src_width = <0x02>;
|
|
|
|
reg_bypass_offset = <0x20>;
|
|
reg_bypass_shift = <0x06>;
|
|
reg_bypass_width = <0x01>;
|
|
|
|
reg_clk_gating_offset = <0x20>;
|
|
reg_clk_gating_shift = <0x04>;
|
|
reg_clk_gating_width = <0x01>;
|
|
|
|
reg_clk_div_m_offset = <0x20>;
|
|
reg_clk_div_m_shift = <0x00>;
|
|
reg_clk_div_m_width = <0x04>;
|
|
|
|
reg_pdzintv_offset = <0x30>;
|
|
reg_pdzintv_shift = <0x08>;
|
|
reg_pdzintv_width = <0x08>;
|
|
|
|
reg_dz_en_offset = <0x30>;
|
|
reg_dz_en_shift = <0x00>;
|
|
reg_dz_en_width = <0x01>;
|
|
|
|
reg_enable_offset = <0x40>;
|
|
reg_enable_shift = <0x01>;
|
|
reg_enable_width = <0x01>;
|
|
|
|
reg_cap_en_offset = <0x44>;
|
|
reg_cap_en_shift = <0x01>;
|
|
reg_cap_en_width = <0x01>;
|
|
|
|
reg_period_rdy_offset = <0x80>;
|
|
reg_period_rdy_shift = <0x0b>;
|
|
reg_period_rdy_width = <0x01>;
|
|
|
|
reg_pul_start_offset = <0x80>;
|
|
reg_pul_start_shift = <0x0a>;
|
|
reg_pul_start_width = <0x01>;
|
|
|
|
reg_mode_offset = <0x80>;
|
|
reg_mode_shift = <0x09>;
|
|
reg_mode_width = <0x01>;
|
|
|
|
reg_act_sta_offset = <0x80>;
|
|
reg_act_sta_shift = <0x08>;
|
|
reg_act_sta_width = <0x01>;
|
|
|
|
reg_prescal_offset = <0x80>;
|
|
reg_prescal_shift = <0x00>;
|
|
reg_prescal_width = <0x08>;
|
|
|
|
reg_entire_offset = <0x84>;
|
|
reg_entire_shift = <0x10>;
|
|
reg_entire_width = <0x10>;
|
|
|
|
reg_active_offset = <0x84>;
|
|
reg_active_shift = <0x00>;
|
|
reg_active_width = <0x10>;
|
|
|
|
};
|
|
pwm2: pwm2@0300a000 {
|
|
compatible = "allwinner,sunxi-pwm2";
|
|
pinctrl-names = "active", "sleep";
|
|
pinctrl-0 = <&pwm2_pins_a>;
|
|
pinctrl-1 = <&pwm2_pins_b>;
|
|
reg_base = <0x0300a000>;
|
|
reg_peci_offset = <0x00>;
|
|
reg_peci_shift = <0x02>;
|
|
reg_peci_width = <0x01>;
|
|
|
|
reg_pis_offset = <0x04>;
|
|
reg_pis_shift = <0x02>;
|
|
reg_pis_width = <0x01>;
|
|
|
|
reg_crie_offset = <0x10>;
|
|
reg_crie_shift = <0x04>;
|
|
reg_crie_width = <0x01>;
|
|
|
|
reg_cfie_offset = <0x10>;
|
|
reg_cfie_shift = <0x05>;
|
|
reg_cfie_width = <0x01>;
|
|
|
|
reg_cris_offset = <0x14>;
|
|
reg_cris_shift = <0x04>;
|
|
reg_cris_width = <0x01>;
|
|
|
|
reg_cfis_offset = <0x14>;
|
|
reg_cfis_shift = <0x05>;
|
|
reg_cfis_width = <0x01>;
|
|
|
|
reg_clk_src_offset = <0x24>;
|
|
reg_clk_src_shift = <0x07>;
|
|
reg_clk_src_width = <0x02>;
|
|
|
|
reg_bypass_offset = <0x24>;
|
|
reg_bypass_shift = <0x06>;
|
|
reg_bypass_width = <0x01>;
|
|
|
|
reg_clk_gating_offset = <0x24>;
|
|
reg_clk_gating_shift = <0x04>;
|
|
reg_clk_gating_width = <0x01>;
|
|
|
|
reg_clk_div_m_offset = <0x24>;
|
|
reg_clk_div_m_shift = <0x00>;
|
|
reg_clk_div_m_width = <0x04>;
|
|
|
|
reg_pdzintv_offset = <0x34>;
|
|
reg_pdzintv_shift = <0x08>;
|
|
reg_pdzintv_width = <0x08>;
|
|
|
|
reg_dz_en_offset = <0x34>;
|
|
reg_dz_en_shift = <0x00>;
|
|
reg_dz_en_width = <0x01>;
|
|
|
|
reg_enable_offset = <0x40>;
|
|
reg_enable_shift = <0x02>;
|
|
reg_enable_width = <0x01>;
|
|
|
|
reg_cap_en_offset = <0x44>;
|
|
reg_cap_en_shift = <0x02>;
|
|
reg_cap_en_width = <0x01>;
|
|
|
|
reg_period_rdy_offset = <0xa0>;
|
|
reg_period_rdy_shift = <0x0b>;
|
|
reg_period_rdy_width = <0x01>;
|
|
|
|
reg_pul_start_offset = <0xa0>;
|
|
reg_pul_start_shift = <0x0a>;
|
|
reg_pul_start_width = <0x01>;
|
|
|
|
reg_mode_offset = <0xa0>;
|
|
reg_mode_shift = <0x09>;
|
|
reg_mode_width = <0x01>;
|
|
|
|
reg_act_sta_offset = <0xa0>;
|
|
reg_act_sta_shift = <0x08>;
|
|
reg_act_sta_width = <0x01>;
|
|
|
|
reg_prescal_offset = <0xa0>;
|
|
reg_prescal_shift = <0x00>;
|
|
reg_prescal_width = <0x08>;
|
|
|
|
reg_entire_offset = <0xa4>;
|
|
reg_entire_shift = <0x10>;
|
|
reg_entire_width = <0x10>;
|
|
|
|
reg_active_offset = <0xa4>;
|
|
reg_active_shift = <0x00>;
|
|
reg_active_width = <0x10>;
|
|
|
|
};
|
|
|
|
pwm3: pwm3@0300a000 {
|
|
compatible = "allwinner,sunxi-pwm3";
|
|
pinctrl-names = "active", "sleep";
|
|
pinctrl-0 = <&pwm3_pins_a>;
|
|
pinctrl-1 = <&pwm3_pins_b>;
|
|
reg_base = <0x0300a000>;
|
|
reg_peci_offset = <0x00>;
|
|
reg_peci_shift = <0x03>;
|
|
reg_peci_width = <0x01>;
|
|
|
|
reg_pis_offset = <0x04>;
|
|
reg_pis_shift = <0x04>;
|
|
reg_pis_width = <0x01>;
|
|
|
|
reg_crie_offset = <0x10>;
|
|
reg_crie_shift = <0x06>;
|
|
reg_crie_width = <0x01>;
|
|
|
|
reg_cfie_offset = <0x10>;
|
|
reg_cfie_shift = <0x07>;
|
|
reg_cfie_width = <0x01>;
|
|
|
|
reg_cris_offset = <0x14>;
|
|
reg_cris_shift = <0x06>;
|
|
reg_cris_width = <0x01>;
|
|
|
|
reg_cfis_offset = <0x14>;
|
|
reg_cfis_shift = <0x07>;
|
|
reg_cfis_width = <0x01>;
|
|
|
|
reg_clk_src_offset = <0x24>;
|
|
reg_clk_src_shift = <0x07>;
|
|
reg_clk_src_width = <0x02>;
|
|
|
|
reg_bypass_offset = <0x24>;
|
|
reg_bypass_shift = <0x06>;
|
|
reg_bypass_width = <0x01>;
|
|
|
|
reg_clk_gating_offset = <0x24>;
|
|
reg_clk_gating_shift = <0x04>;
|
|
reg_clk_gating_width = <0x01>;
|
|
|
|
reg_clk_div_m_offset = <0x24>;
|
|
reg_clk_div_m_shift = <0x00>;
|
|
reg_clk_div_m_width = <0x04>;
|
|
|
|
reg_pdzintv_offset = <0x34>;
|
|
reg_pdzintv_shift = <0x08>;
|
|
reg_pdzintv_width = <0x08>;
|
|
|
|
reg_dz_en_offset = <0x34>;
|
|
reg_dz_en_shift = <0x00>;
|
|
reg_dz_en_width = <0x01>;
|
|
|
|
reg_enable_offset = <0x40>;
|
|
reg_enable_shift = <0x03>;
|
|
reg_enable_width = <0x01>;
|
|
|
|
reg_cap_en_offset = <0x44>;
|
|
reg_cap_en_shift = <0x03>;
|
|
reg_cap_en_width = <0x01>;
|
|
|
|
reg_period_rdy_offset = <0xc0>;
|
|
reg_period_rdy_shift = <0x0b>;
|
|
reg_period_rdy_width = <0x01>;
|
|
|
|
reg_pul_start_offset = <0xc0>;
|
|
reg_pul_start_shift = <0x0a>;
|
|
reg_pul_start_width = <0x01>;
|
|
|
|
reg_mode_offset = <0xc0>;
|
|
reg_mode_shift = <0x09>;
|
|
reg_mode_width = <0x01>;
|
|
|
|
reg_act_sta_offset = <0xc0>;
|
|
reg_act_sta_shift = <0x08>;
|
|
reg_act_sta_width = <0x01>;
|
|
|
|
reg_prescal_offset = <0xc0>;
|
|
reg_prescal_shift = <0x00>;
|
|
reg_prescal_width = <0x08>;
|
|
|
|
reg_entire_offset = <0xc4>;
|
|
reg_entire_shift = <0x10>;
|
|
reg_entire_width = <0x10>;
|
|
|
|
reg_active_offset = <0xc4>;
|
|
reg_active_shift = <0x00>;
|
|
reg_active_width = <0x10>;
|
|
|
|
};
|
|
|
|
pwm4: pwm4@0300a000 {
|
|
compatible = "allwinner,sunxi-pwm4";
|
|
pinctrl-names = "active", "sleep";
|
|
pinctrl-0 = <&pwm4_pins_a>;
|
|
pinctrl-1 = <&pwm4_pins_b>;
|
|
reg_base = <0x0300a000>;
|
|
reg_peci_offset = <0x00>;
|
|
reg_peci_shift = <0x04>;
|
|
reg_peci_width = <0x01>;
|
|
|
|
reg_pis_offset = <0x04>;
|
|
reg_pis_shift = <0x04>;
|
|
reg_pis_width = <0x01>;
|
|
|
|
reg_crie_offset = <0x10>;
|
|
reg_crie_shift = <0x08>;
|
|
reg_crie_width = <0x01>;
|
|
|
|
reg_cfie_offset = <0x10>;
|
|
reg_cfie_shift = <0x09>;
|
|
reg_cfie_width = <0x01>;
|
|
|
|
reg_cris_offset = <0x14>;
|
|
reg_cris_shift = <0x08>;
|
|
reg_cris_width = <0x01>;
|
|
|
|
reg_cfis_offset = <0x14>;
|
|
reg_cfis_shift = <0x09>;
|
|
reg_cfis_width = <0x01>;
|
|
|
|
reg_clk_src_offset = <0x28>;
|
|
reg_clk_src_shift = <0x07>;
|
|
reg_clk_src_width = <0x02>;
|
|
|
|
reg_bypass_offset = <0x28>;
|
|
reg_bypass_shift = <0x06>;
|
|
reg_bypass_width = <0x01>;
|
|
|
|
reg_clk_gating_offset = <0x28>;
|
|
reg_clk_gating_shift = <0x04>;
|
|
reg_clk_gating_width = <0x01>;
|
|
|
|
reg_clk_div_m_offset = <0x28>;
|
|
reg_clk_div_m_shift = <0x00>;
|
|
reg_clk_div_m_width = <0x04>;
|
|
|
|
reg_pdzintv_offset = <0x38>;
|
|
reg_pdzintv_shift = <0x08>;
|
|
reg_pdzintv_width = <0x08>;
|
|
|
|
reg_dz_en_offset = <0x38>;
|
|
reg_dz_en_shift = <0x00>;
|
|
reg_dz_en_width = <0x01>;
|
|
|
|
reg_enable_offset = <0x40>;
|
|
reg_enable_shift = <0x04>;
|
|
reg_enable_width = <0x01>;
|
|
|
|
reg_cap_en_offset = <0x44>;
|
|
reg_cap_en_shift = <0x04>;
|
|
reg_cap_en_width = <0x01>;
|
|
|
|
reg_period_rdy_offset = <0xe0>;
|
|
reg_period_rdy_shift = <0x0b>;
|
|
reg_period_rdy_width = <0x01>;
|
|
|
|
reg_pul_start_offset = <0xe0>;
|
|
reg_pul_start_shift = <0x0a>;
|
|
reg_pul_start_width = <0x01>;
|
|
|
|
reg_mode_offset = <0xe0>;
|
|
reg_mode_shift = <0x09>;
|
|
reg_mode_width = <0x01>;
|
|
|
|
reg_act_sta_offset = <0xe0>;
|
|
reg_act_sta_shift = <0x08>;
|
|
reg_act_sta_width = <0x01>;
|
|
|
|
reg_prescal_offset = <0xe0>;
|
|
reg_prescal_shift = <0x00>;
|
|
reg_prescal_width = <0x08>;
|
|
|
|
reg_entire_offset = <0xe4>;
|
|
reg_entire_shift = <0x10>;
|
|
reg_entire_width = <0x10>;
|
|
|
|
reg_active_offset = <0xe4>;
|
|
reg_active_shift = <0x00>;
|
|
reg_active_width = <0x10>;
|
|
|
|
};
|
|
|
|
pwm5: pwm5@0300a000 {
|
|
compatible = "allwinner,sunxi-pwm5";
|
|
pinctrl-names = "active", "sleep";
|
|
pinctrl-0 = <&pwm5_pins_a>;
|
|
pinctrl-1 = <&pwm5_pins_b>;
|
|
reg_base = <0x0300a000>;
|
|
reg_peci_offset = <0x00>;
|
|
reg_peci_shift = <0x05>;
|
|
reg_peci_width = <0x01>;
|
|
|
|
reg_pis_offset = <0x04>;
|
|
reg_pis_shift = <0x05>;
|
|
reg_pis_width = <0x01>;
|
|
|
|
reg_crie_offset = <0x10>;
|
|
reg_crie_shift = <0x0a>;
|
|
reg_crie_width = <0x01>;
|
|
|
|
reg_cfie_offset = <0x10>;
|
|
reg_cfie_shift = <0x0b>;
|
|
reg_cfie_width = <0x01>;
|
|
|
|
reg_cris_offset = <0x14>;
|
|
reg_cris_shift = <0x0a>;
|
|
reg_cris_width = <0x01>;
|
|
|
|
reg_cfis_offset = <0x14>;
|
|
reg_cfis_shift = <0x0b>;
|
|
reg_cfis_width = <0x01>;
|
|
|
|
reg_clk_src_offset = <0x28>;
|
|
reg_clk_src_shift = <0x07>;
|
|
reg_clk_src_width = <0x02>;
|
|
|
|
reg_bypass_offset = <0x28>;
|
|
reg_bypass_shift = <0x06>;
|
|
reg_bypass_width = <0x01>;
|
|
|
|
reg_clk_gating_offset = <0x28>;
|
|
reg_clk_gating_shift = <0x04>;
|
|
reg_clk_gating_width = <0x01>;
|
|
|
|
reg_clk_div_m_offset = <0x28>;
|
|
reg_clk_div_m_shift = <0x00>;
|
|
reg_clk_div_m_width = <0x04>;
|
|
|
|
reg_pdzintv_offset = <0x38>;
|
|
reg_pdzintv_shift = <0x08>;
|
|
reg_pdzintv_width = <0x08>;
|
|
|
|
reg_dz_en_offset = <0x38>;
|
|
reg_dz_en_shift = <0x00>;
|
|
reg_dz_en_width = <0x01>;
|
|
|
|
reg_enable_offset = <0x40>;
|
|
reg_enable_shift = <0x05>;
|
|
reg_enable_width = <0x01>;
|
|
|
|
reg_cap_en_offset = <0x44>;
|
|
reg_cap_en_shift = <0x05>;
|
|
reg_cap_en_width = <0x01>;
|
|
|
|
reg_period_rdy_offset = <0x100>;
|
|
reg_period_rdy_shift = <0x0b>;
|
|
reg_period_rdy_width = <0x01>;
|
|
|
|
reg_pul_start_offset = <0x100>;
|
|
reg_pul_start_shift = <0x0a>;
|
|
reg_pul_start_width = <0x01>;
|
|
|
|
reg_mode_offset = <0x100>;
|
|
reg_mode_shift = <0x09>;
|
|
reg_mode_width = <0x01>;
|
|
|
|
reg_act_sta_offset = <0x100>;
|
|
reg_act_sta_shift = <0x08>;
|
|
reg_act_sta_width = <0x01>;
|
|
|
|
reg_prescal_offset = <0x100>;
|
|
reg_prescal_shift = <0x00>;
|
|
reg_prescal_width = <0x08>;
|
|
|
|
reg_entire_offset = <0x104>;
|
|
reg_entire_shift = <0x10>;
|
|
reg_entire_width = <0x10>;
|
|
|
|
reg_active_offset = <0x104>;
|
|
reg_active_shift = <0x00>;
|
|
reg_active_width = <0x10>;
|
|
|
|
};
|
|
|
|
pwm6: pwm6@0300a000 {
|
|
compatible = "allwinner,sunxi-pwm6";
|
|
pinctrl-names = "active", "sleep";
|
|
pinctrl-0 = <&pwm6_pins_a>;
|
|
pinctrl-1 = <&pwm6_pins_b>;
|
|
reg_base = <0x0300a000>;
|
|
reg_peci_offset = <0x00>;
|
|
reg_peci_shift = <0x06>;
|
|
reg_peci_width = <0x01>;
|
|
|
|
reg_pis_offset = <0x04>;
|
|
reg_pis_shift = <0x06>;
|
|
reg_pis_width = <0x01>;
|
|
|
|
reg_crie_offset = <0x10>;
|
|
reg_crie_shift = <0x0c>;
|
|
reg_crie_width = <0x01>;
|
|
|
|
reg_cfie_offset = <0x10>;
|
|
reg_cfie_shift = <0x0d>;
|
|
reg_cfie_width = <0x01>;
|
|
|
|
reg_cris_offset = <0x14>;
|
|
reg_cris_shift = <0x0c>;
|
|
reg_cris_width = <0x01>;
|
|
|
|
reg_cfis_offset = <0x14>;
|
|
reg_cfis_shift = <0x0d>;
|
|
reg_cfis_width = <0x01>;
|
|
|
|
reg_clk_src_offset = <0x2c>;
|
|
reg_clk_src_shift = <0x07>;
|
|
reg_clk_src_width = <0x02>;
|
|
|
|
reg_bypass_offset = <0x2c>;
|
|
reg_bypass_shift = <0x06>;
|
|
reg_bypass_width = <0x01>;
|
|
|
|
reg_clk_gating_offset = <0x2c>;
|
|
reg_clk_gating_shift = <0x04>;
|
|
reg_clk_gating_width = <0x01>;
|
|
|
|
reg_clk_div_m_offset = <0x2c>;
|
|
reg_clk_div_m_shift = <0x00>;
|
|
reg_clk_div_m_width = <0x04>;
|
|
|
|
reg_pdzintv_offset = <0x3c>;
|
|
reg_pdzintv_shift = <0x08>;
|
|
reg_pdzintv_width = <0x08>;
|
|
|
|
reg_dz_en_offset = <0x3c>;
|
|
reg_dz_en_shift = <0x00>;
|
|
reg_dz_en_width = <0x01>;
|
|
|
|
reg_enable_offset = <0x40>;
|
|
reg_enable_shift = <0x06>;
|
|
reg_enable_width = <0x01>;
|
|
|
|
reg_cap_en_offset = <0x44>;
|
|
reg_cap_en_shift = <0x06>;
|
|
reg_cap_en_width = <0x01>;
|
|
|
|
reg_period_rdy_offset = <0x120>;
|
|
reg_period_rdy_shift = <0x0b>;
|
|
reg_period_rdy_width = <0x01>;
|
|
|
|
reg_pul_start_offset = <0x120>;
|
|
reg_pul_start_shift = <0x0a>;
|
|
reg_pul_start_width = <0x01>;
|
|
|
|
reg_mode_offset = <0x120>;
|
|
reg_mode_shift = <0x09>;
|
|
reg_mode_width = <0x01>;
|
|
|
|
reg_act_sta_offset = <0x120>;
|
|
reg_act_sta_shift = <0x08>;
|
|
reg_act_sta_width = <0x01>;
|
|
|
|
reg_prescal_offset = <0x120>;
|
|
reg_prescal_shift = <0x00>;
|
|
reg_prescal_width = <0x08>;
|
|
|
|
reg_entire_offset = <0x124>;
|
|
reg_entire_shift = <0x10>;
|
|
reg_entire_width = <0x10>;
|
|
|
|
reg_active_offset = <0x124>;
|
|
reg_active_shift = <0x00>;
|
|
reg_active_width = <0x10>;
|
|
|
|
};
|
|
|
|
pwm7: pwm7@0300a000 {
|
|
compatible = "allwinner,sunxi-pwm7";
|
|
pinctrl-names = "active", "sleep";
|
|
pinctrl-0 = <&pwm7_pins_a>;
|
|
pinctrl-1 = <&pwm7_pins_b>;
|
|
reg_base = <0x0300a000>;
|
|
reg_peci_offset = <0x00>;
|
|
reg_peci_shift = <0x07>;
|
|
reg_peci_width = <0x01>;
|
|
|
|
reg_pis_offset = <0x04>;
|
|
reg_pis_shift = <0x07>;
|
|
reg_pis_width = <0x01>;
|
|
|
|
reg_crie_offset = <0x10>;
|
|
reg_crie_shift = <0x0e>;
|
|
reg_crie_width = <0x01>;
|
|
|
|
reg_cfie_offset = <0x10>;
|
|
reg_cfie_shift = <0x0f>;
|
|
reg_cfie_width = <0x01>;
|
|
|
|
reg_cris_offset = <0x14>;
|
|
reg_cris_shift = <0x0e>;
|
|
reg_cris_width = <0x01>;
|
|
|
|
reg_cfis_offset = <0x14>;
|
|
reg_cfis_shift = <0x0f>;
|
|
reg_cfis_width = <0x01>;
|
|
|
|
reg_clk_src_offset = <0x2c>;
|
|
reg_clk_src_shift = <0x07>;
|
|
reg_clk_src_width = <0x02>;
|
|
|
|
reg_bypass_offset = <0x2c>;
|
|
reg_bypass_shift = <0x06>;
|
|
reg_bypass_width = <0x01>;
|
|
|
|
reg_clk_gating_offset = <0x2c>;
|
|
reg_clk_gating_shift = <0x04>;
|
|
reg_clk_gating_width = <0x01>;
|
|
|
|
reg_clk_div_m_offset = <0x2c>;
|
|
reg_clk_div_m_shift = <0x00>;
|
|
reg_clk_div_m_width = <0x04>;
|
|
|
|
reg_pdzintv_offset = <0x3c>;
|
|
reg_pdzintv_shift = <0x08>;
|
|
reg_pdzintv_width = <0x08>;
|
|
|
|
reg_dz_en_offset = <0x3c>;
|
|
reg_dz_en_shift = <0x00>;
|
|
reg_dz_en_width = <0x01>;
|
|
|
|
reg_enable_offset = <0x40>;
|
|
reg_enable_shift = <0x07>;
|
|
reg_enable_width = <0x01>;
|
|
|
|
reg_cap_en_offset = <0x44>;
|
|
reg_cap_en_shift = <0x07>;
|
|
reg_cap_en_width = <0x01>;
|
|
|
|
reg_period_rdy_offset = <0x140>;
|
|
reg_period_rdy_shift = <0x0b>;
|
|
reg_period_rdy_width = <0x01>;
|
|
|
|
reg_pul_start_offset = <0x140>;
|
|
reg_pul_start_shift = <0x0a>;
|
|
reg_pul_start_width = <0x01>;
|
|
|
|
reg_mode_offset = <0x140>;
|
|
reg_mode_shift = <0x09>;
|
|
reg_mode_width = <0x01>;
|
|
|
|
reg_act_sta_offset = <0x140>;
|
|
reg_act_sta_shift = <0x08>;
|
|
reg_act_sta_width = <0x01>;
|
|
|
|
reg_prescal_offset = <0x140>;
|
|
reg_prescal_shift = <0x00>;
|
|
reg_prescal_width = <0x08>;
|
|
|
|
reg_entire_offset = <0x144>;
|
|
reg_entire_shift = <0x10>;
|
|
reg_entire_width = <0x10>;
|
|
|
|
reg_active_offset = <0x144>;
|
|
reg_active_shift = <0x00>;
|
|
reg_active_width = <0x10>;
|
|
|
|
};
|
|
|
|
boot_disp: boot_disp {
|
|
compatible = "allwinner,boot_disp";
|
|
};
|
|
|
|
|
|
|
|
|
|
nand0:nand0@04011000 {
|
|
compatible = "allwinner,sun8iw18-nand";
|
|
device_type = "nand0";
|
|
reg = <0x0 0x04011000 0x0 0x1000>; /* nand0 */
|
|
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
|
|
/*clocks = <&clk_pll_periph1x2>,<&clk_nand0>,<&clk_nand1>;*/
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&nand0_pins_a &nand0_pins_b>;
|
|
pinctrl-1 = <&nand0_pins_c>;
|
|
nand0_regulator1 = "vcc-nand";
|
|
nand0_regulator2 = "none";
|
|
nand0_cache_level = <0x55aaaa55>;
|
|
nand0_flush_cache_num = <0x55aaaa55>;
|
|
nand0_capacity_level = <0x55aaaa55>;
|
|
nand0_id_number_ctl = <0x55aaaa55>;
|
|
nand0_print_level = <0x55aaaa55>;
|
|
nand0_p0 = <0x55aaaa55>;
|
|
nand0_p1 = <0x55aaaa55>;
|
|
nand0_p2 = <0x55aaaa55>;
|
|
nand0_p3 = <0x55aaaa55>;
|
|
status = "disabled";
|
|
};
|
|
|
|
|
|
ledc: ledc@0x06700000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "allwinner,sunxi-leds";
|
|
reg = <0x0 0x06700000 0x0 0x50>;
|
|
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "ledcirq";
|
|
/*clocks = <&clk_ledc>, <&clk_cpuapb>;*/
|
|
clock-names = "clk_ledc", "clk_cpuapb";
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&ledc_pins_a>;
|
|
pinctrl-1 = <&ledc_pins_b>;
|
|
led_count = <32>;
|
|
output_mode = "GRB";
|
|
reset_ns = <84>;
|
|
t1h_ns = <800>;
|
|
t1l_ns = <450>;
|
|
t0h_ns = <400>;
|
|
t0l_ns = <850>;
|
|
wait_time0_ns = <84>;
|
|
wait_time1_ns = <84>;
|
|
wait_data_time_ns = <600000>;
|
|
};
|
|
};
|
|
};
|