150 lines
4.1 KiB
Plaintext
150 lines
4.1 KiB
Plaintext
/{
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clocks {
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compatible = "allwinner,clk-init";
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device_type = "clocks";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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reg = <0x0 0x02001000 0x0 0x1000>, /* cpux-ccu space */
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<0x0 0x07010000 0x0 0x400>, /* cpus-ccu space */
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<0x0 0x07090000 0x0 0x400>; /* rtc-ccu space */
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/* register factor clock */
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clk_pll_periph0: pll_periph0 {
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#clock-cells = <0>;
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compatible = "allwinner,pll-clock";
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assigned-clock-rates = <600000000>;
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lock-mode = "new";
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clock-output-names = "pll_periph0";
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};
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clk_pll_video0x4: pll_video0x4 {
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#clock-cells = <0>;
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compatible = "allwinner,pll-clock";
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lock-mode = "new";
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clock-output-names = "pll_video0x4";
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};
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clk_pll_video2: pll_video2 {
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#clock-cells = <0>;
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compatible = "allwinner,pll-clock";
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lock-mode = "new";
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assigned-clocks = <&clk_pll_video2>;
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assigned-clock-rates = <336000000>;
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clock-output-names = "pll_video2";
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};
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clk_pll_csix4: pll_csix4 {
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#clock-cells = <0>;
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compatible = "allwinner,pll-clock";
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assigned-clock-rates = <1188000000>;
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lock-mode = "new";
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clock-output-names = "pll_csix4";
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};
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/* register fix_factor clock */
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/* specify parent of clocks in clk-sun8iw21.c, not here */
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clk_pll_video0: pll_video0 {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-factor-clock";
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clock-mult = <1>;
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clock-div = <4>;
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clock-output-names = "pll_video0";
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};
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clk_pll_periph0x2: pll_periph0x2 {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-factor-clock";
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clock-mult = <2>;
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clock-div = <1>;
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clock-output-names = "pll_periph0x2";
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};
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clk_pll_periph0600m: pll_periph0600m {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-factor-clock";
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clock-mult = <1>;
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clock-div = <2>;
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clock-output-names = "pll_periph0600m";
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};
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clk_pll_periph0400m: pll_periph0400m {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-factor-clock";
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clock-mult = <1>;
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clock-div = <3>;
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clock-output-names = "pll_periph0400m";
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};
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clk_pll_periph0200m: pll_periph0200m {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-factor-clock";
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clock-mult = <1>;
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clock-div = <2>;
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clock-output-names = "pll_periph0200m";
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};
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clk_pll_periph0300m: pll_periph0300m {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-factor-clock";
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clock-mult = <1>;
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clock-div = <2>;
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clock-output-names = "pll_periph0300m";
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};
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clk_pll_periph0150m: pll_periph0150m {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-factor-clock";
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clock-mult = <1>;
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clock-div = <2>;
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clock-output-names = "pll_periph0150m";
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};
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/* register periph clock */
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clk_de0: de0 {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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assigned-clock-parents = <&clk_pll_periph0x2>;
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assigned-clock-rates = <300000000>;
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assigned-clocks = <&clk_de0>;
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clock-output-names = "de0";
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};
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clk_ee: ee {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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assigned-clock-parents = <&clk_pll_periph0x2>;
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assigned-clock-rates = <300000000>;
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assigned-clocks = <&clk_ee>;
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clock-output-names = "ee";
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};
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clk_panel: panel {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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assigned-clock-parents = <&clk_pll_video2>;
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assigned-clock-rates = <30000000>;
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assigned-clocks = <&clk_panel>;
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clock-output-names = "panel";
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};
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clk_de: de {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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assigned-clock-rates = <300000000>;
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clock-output-names = "de";
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};
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clk_ahb: ahb {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "ahb";
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};
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clk_dpss_top: dpss_top {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "dpss_top";
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};
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clk_tcon_lcd: tcon_lcd {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "tcon_lcd";
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};
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clk_mipi_dsi: mipi_dsi {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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assigned-clocks = <&clk_mipi_dsi>;
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assigned-clock-parents = <&clk_pll_periph0150m>;
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// assigned-clock-rates = <150000000>;
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clock-output-names = "mipi_dsi";
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};
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};
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};
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