154 lines
3.6 KiB
C
154 lines
3.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2007-2011
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Tom Cubie <tangliang@allwinnertech.com>
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/gpio.h>
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void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val)
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{
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u32 index = GPIO_CFG_INDEX(bank_offset);
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u32 offset = GPIO_CFG_OFFSET(bank_offset);
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clrsetbits_le32(&pio->cfg[0] + index, 0xf << offset, val << offset);
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}
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void sunxi_gpio_set_cfgpin(u32 pin, u32 val)
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{
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u32 bank = GPIO_BANK(pin);
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struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
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sunxi_gpio_set_cfgbank(pio, pin, val);
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}
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int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset)
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{
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u32 index = GPIO_CFG_INDEX(bank_offset);
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u32 offset = GPIO_CFG_OFFSET(bank_offset);
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u32 cfg;
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cfg = readl(&pio->cfg[0] + index);
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cfg >>= offset;
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return cfg & 0xf;
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}
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int sunxi_gpio_get_cfgpin(u32 pin)
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{
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u32 bank = GPIO_BANK(pin);
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struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
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return sunxi_gpio_get_cfgbank(pio, pin);
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}
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int sunxi_gpio_set_drv(u32 pin, u32 val)
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{
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u32 bank = GPIO_BANK(pin);
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u32 index = GPIO_DRV_INDEX(pin);
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u32 offset = GPIO_DRV_OFFSET(pin);
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struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
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clrsetbits_le32(&pio->drv[0] + index, 0x3 << offset, val << offset);
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return 0;
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}
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int sunxi_gpio_set_pull(u32 pin, u32 val)
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{
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u32 bank = GPIO_BANK(pin);
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u32 index = GPIO_PULL_INDEX(pin);
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u32 offset = GPIO_PULL_OFFSET(pin);
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struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
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clrsetbits_le32(&pio->pull[0] + index, 0x3 << offset, val << offset);
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return 0;
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}
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#if defined(PIOC_REG_POW_MS_CTL) && \
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defined (PIOC_REG_POW_MOD_SEL) && \
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defined (PIOC_REG_POW_VAL)
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__weak int get_group_bit_offset(enum pin_e port_group)
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{
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return -1;
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}
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void io_pow_mode_disable(enum pin_e port_group)
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{
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uint32_t reg;
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uint8_t group_bit_offset = get_group_bit_offset(port_group);
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if (group_bit_offset < 0)
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return;
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//disable auto mode
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reg = readl(PIOC_REG_POW_MS_CTL);
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reg |= (1 << group_bit_offset);
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writel(reg, PIOC_REG_POW_MS_CTL);
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}
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enum io_pow_mode_e io_get_volt_val(enum pin_e port_group)
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{
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uint32_t reg;
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uint8_t group_bit_offset = get_group_bit_offset(port_group);
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if (group_bit_offset < 0)
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return IO_MODE_DEFAULT;
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reg = readl(PIOC_REG_POW_VAL);
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return ((reg & (1 << group_bit_offset)) != 0) ? IO_MODE_1_8_V :
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IO_MODE_3_3_V;
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}
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void io_set_pow_mode(enum pin_e port_group, enum io_pow_mode_e volt_mode)
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{
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uint32_t reg;
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uint8_t group_bit_offset = get_group_bit_offset(port_group);
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if (group_bit_offset < 0)
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return;
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if (volt_mode == IO_MODE_DEFAULT) {
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//default vaule in spec
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reg = readl(PIOC_REG_POW_MS_CTL);
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reg &= ~(1 << group_bit_offset);
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writel(reg, PIOC_REG_POW_MS_CTL);
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reg = readl(PIOC_REG_POW_MOD_SEL);
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reg &= ~(1 << group_bit_offset);
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writel(reg, PIOC_REG_POW_MOD_SEL);
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} else if (volt_mode == IO_MODE_AUTO) {
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//one specific combination is auto
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reg = readl(PIOC_REG_POW_MS_CTL);
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reg &= ~(1 << group_bit_offset);
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writel(reg, PIOC_REG_POW_MS_CTL);
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reg = readl(PIOC_REG_POW_MOD_SEL);
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reg |= (1 << group_bit_offset);
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writel(reg, PIOC_REG_POW_MOD_SEL);
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} else {
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if (volt_mode == IO_MODE_1_8_V) {
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reg = readl(PIOC_REG_POW_MOD_SEL);
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reg |= (1 << group_bit_offset);
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writel(reg, PIOC_REG_POW_MOD_SEL);
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} else {
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reg = readl(PIOC_REG_POW_MOD_SEL);
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reg &= ~(1 << group_bit_offset);
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writel(reg, PIOC_REG_POW_MOD_SEL);
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}
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}
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}
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void sunxi_io_set_pow_mode_on_actual_val(enum pin_e port_group)
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{
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io_pow_mode_disable(port_group);
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io_set_pow_mode(port_group, io_get_volt_val(port_group));
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}
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void sunxi_io_set_pow_mode_to_default(enum pin_e port_group)
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{
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io_set_pow_mode(port_group, IO_MODE_DEFAULT);
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}
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#endif
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