198 lines
6.8 KiB
C
198 lines
6.8 KiB
C
/*
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* Copyright (C) 2013 Allwinnertech, huangshuosheng <huangshuosheng@allwinnertech.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Adjustable factor-based clock implementation
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*/
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#ifndef __MACH_SUNXI_CLK_SUN55IW3_H
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#define __MACH_SUNXI_CLK_SUN55IW3_H
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#include "clk_factor.h"
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/* CCMU Register List */
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#define PLL_CPU 0x0000
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#define PLL_DDR 0x0010
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#define PLL_PERIPH0 0x0020
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#define PLL_PERIPH1 0x0028
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#define PLL_GPU 0x0030
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#define PLL_VIDEO0 0x0040
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#define PLL_VIDEO1 0x0048
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#define PLL_VIDEO2 0x0050
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#define PLL_VE 0x0058
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#define PLL_COM 0x0060
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#define PLL_VIDEO3 0x0068
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#define PLL_AUDIO 0x0078
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#define PLL_DDRPAT 0x0110
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#define PLL_PERI0PAT0 0x0120
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#define PLL_PERI0PAT1 0x0124
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#define PLL_PERI1PAT0 0x0128
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#define PLL_PERI1PAT1 0x012C
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#define PLL_GPUPAT0 0x0130
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#define PLL_GPUPAT1 0x0134
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#define PLL_VIDEO0PAT0 0x0140
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#define PLL_VIDEO0PAT1 0x0144
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#define PLL_VIDEO1PAT0 0x0148
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#define PLL_VIDEO1PAT1 0x014C
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#define PLL_VIDEO2PAT0 0x0150
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#define PLL_VIDEO2PAT1 0x0154
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#define PLL_VEPAT0 0x0158
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#define PLL_VEPAT1 0x015C
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#define PLL_COMPAT0 0x0160
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#define PLL_COMPAT1 0x0164
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#define PLL_VIDEO3PAT0 0x016c
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#define PLL_AUDIOPAT0 0x0178
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#define PLL_AUDIOPAT1 0x017C
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#define PLL_VE_BIAS_REG 0x0358
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#define CPU_CFG 0x0500
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#define PSI_CFG 0x0510
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#define AHB3_CFG 0x051C
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#define APB1_CFG 0x0520
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#define APB2_CFG 0x0524
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#define MBUS_CFG 0x0540
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/* Accelerator */
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#define DE0_CFG 0x0600
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#define DE1_CFG 0x0604
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#define DE_GATE 0x060C
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#define EE_CFG 0x0610
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#define EINK_GATE 0x061C
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#define PANEL_CFG 0x0640
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#define G2D_CFG 0x0630
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#define G2D_GATE 0x063C
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#define GPU_CFG 0x0670
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#define GPU_GATE 0x067C
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#define CE_CFG 0x0680
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#define CE_GATE 0x068C
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#define VE_CFG 0x0690
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#define VE_GATE 0x069C
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/* SYS Resource */
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#define DMA_GATE 0x070C
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#define MSGBOX_GATE 0x071C
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#define SPINLOCK_GATE 0x072C
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#define HSTIMER_GATE 0x073C
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#define AVS_CFG 0x0740
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#define DBGSYS_GATE 0x078C
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#define PSI_GATE 0x079C
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#define PWM_GATE 0x07AC
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#define IOMMU_GATE 0x07BC
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/* Storage Medium */
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#define DRAM_CFG 0x0800
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#define MBUS_GATE 0x0804
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#define DRAM_GATE 0x080C
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#define NAND0_CFG 0x0810
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#define NAND1_CFG 0x0814
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#define NAND_GATE 0x082C
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#define SMHC0_CFG 0x0830
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#define SMHC1_CFG 0x0834
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#define SMHC2_CFG 0x0838
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#define SMHC3_CFG 0x083C
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#define SMHC_GATE 0x084C
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/* Common Interface */
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#define UART_GATE 0x090C
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#define TWI_GATE 0x091C
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#define SCR_GATE 0x093C
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#define SPI0_CFG 0x0940
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#define SPI1_CFG 0x0944
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#define SPI2_CFG 0x0948
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#define SPI_GATE 0x096C
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#define GMAC0_25M_CFG 0x0970
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#define GMAC1_25M_CFG 0x0974
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#define GMAC_GATE 0x097C
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#define IRRX_CFG 0x0990
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#define IRRX_GATE 0x099C
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#define IRTX_CFG 0x09C0
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#define IRTX_GATE 0x09CC
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#define GPADC_GATE 0x09EC
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#define THS_GATE 0x09FC
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#define I2S0_CFG 0x0A10
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#define I2S1_CFG 0x0A14
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#define I2S2_CFG 0x0A18
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#define I2S3_CFG 0x0A1C
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#define I2S_GATE 0x0A20
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#define SPDIF_CFG 0x0A24
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#define SPDIF_GATE 0x0A2C
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#define DMIC_CFG 0x0A40
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#define DMIC_GATE 0x0A4C
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#define CODEC_DAC_1X_CFG 0x0A50
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#define CODEC_ADC_1X_CFG 0x0A54
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#define CODEC_4X_CFG 0x0A58
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#define CODEC_GATE 0x0A5C
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#define AHUB_CFG 0x0A60
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#define AHUB_GATE 0x0A6C
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#define USB0_CFG 0x0A70
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#define USB1_CFG 0x0A74
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#define USB_GATE 0x0A8C
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#define LRADC_GATE 0x0A9C
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#define LEDC_CFG 0x0BF0
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#define LEDC_GATE 0x0BFC
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/* Display Interface */
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#define DPSS_TOP0_GATE 0x0ABC
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#define DPSS_TOP1_GATE 0x0ACC
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#define DSI_CFG0 0x0B24
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#define DSI_CFG1 0x0B28
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#define DSI_GATE 0x0B4C
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#define DISPLAY_TOP_GATE 0x0B5C
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#define TCON_LCD_CFG0 0x0B60
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#define TCON_LCD_CFG1 0x0B64
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#define TCON_LCD_CFG2 0x0B68
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#define COMBPHY0_CFG 0x0B6C
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#define COMBPHY1_CFG 0x0B70
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#define TCON_LCD_GATE 0x0B7C
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#define TCONTV_CFG 0x0B80
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#define TCONTV_CFG1 0x0B84
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#define TCONTV_GATE 0x0B9c
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#define LVDS_GATE 0x0BAC
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#define CSI_TOP_CFG 0x0C04
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#define CSI_MASTER0_CFG 0x0C08
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#define CSI_MASTER1_CFG 0x0C0C
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#define CSI_GATE 0x0C1C
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#define CSI_ISP_CFG 0x0C20
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#define CSI_ISP_GATE 0x0C2C
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#define SUNXI_CLK_MAX_REG 0x0C2C
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/* PRCM Register List */
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#define CPUS_CFG 0x0000
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#define CPUS_APBS1_CFG 0x000C
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#define CPUS_APBS2_CFG 0x0010
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#define CPUS_TWDOG_GATE 0x012C
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#define CPUS_PPU_GATE 0x017C
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#define CPUS_UART_GATE 0x018C
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#define CPUS_TWI_GATE 0x019C
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#define CPUS_RSB_GATE 0x01BC
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#define CPUS_CIR_CFG 0x01C0
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#define CPUS_CIR_GATE 0x01CC
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#define CPUS_OWC_CFG 0x01E0
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#define CPUS_OWC_GATE 0x01EC
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#define CPUS_RTC_GATE 0x020C
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#define CPUS_CLK_MAX_REG 0x020C
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/* RTC Register List */
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#define LOSC_OUT_GATE 0x0060
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#define DCXO_OUT_CFG 0x0160
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#define F_N8X8_M0X2_P16x2(nv, mv, pv) (FACTOR_ALL(nv, 8, 8, 0, 0, 0, mv, 0, 2, pv, 16, 2, 0, 0, 0, 0, 0, 0))
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#define F_N8X8_D1V1X1_D2V0X1(nv, d1v, d2v) (FACTOR_ALL(nv, 8, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, d1v, 1, 1, d2v, 16, 3))
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#define F_N8X8_D1V1X1_D2V20X3(nv, d1v, d2v) (FACTOR_ALL(nv, 8, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, d1v, 1, 1, d2v, 20, 3))
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#define F_N8X8_D1V1X1_D2V0X0(nv, d1v, d2v) (FACTOR_ALL(nv, 8, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, d1v, 1, 1, d2v, 0, 1))
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#define F_N8X8_D1V4X2_D2V0X2(nv, d1v, d2v) (FACTOR_ALL(nv, 8, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, d1v, 4, 2, d2v, 0, 2))
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#define F_N8X8_P16X6_D1V1X1_D2V0X1(nv, pv, d1v, d2v) (FACTOR_ALL(nv, 8, 8, 0, 0, 0, 0, 0, 0, pv, 16, 6, d1v, 1, 1, d2v, 0, 1))
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#define PLL_PERIPH0_2X(n, d1, d2, freq) {F_N8X8_D1V1X1_D2V0X1(n, d1, d2), freq}
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#define PLL_PERIPH1_2X(n, d1, d2, freq) {F_N8X8_D1V1X1_D2V0X1(n, d1, d2), freq}
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#define PLL_PERIPH1_800M(n, d1, d2, freq) {F_N8X8_D1V1X1_D2V20X3(n, d1, d2), freq}
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#define PLLVIDEO0(n, d1, d2, freq) {F_N8X8_D1V1X1_D2V0X0(n, d1, d2), freq}
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#define PLLVIDEO3(n, d1, d2, freq) {F_N8X8_D1V1X1_D2V0X0(n, d1, d2), freq}
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#endif
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