148 lines
3.3 KiB
C
148 lines
3.3 KiB
C
/*
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* drivers/input/sensor/sunxi_gpadc.h
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*
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* Copyright (C) 2016 Allwinner.
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* fuzhaoke <fuzhaoke@allwinnertech.com>
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*
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* SUNXI GPADC Controller Driver Header
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#ifndef HAL_GPADC_H
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#define HAL_GPADC_H
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#include <hal_clk.h>
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#include <hal_reset.h>
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#include "sunxi_hal_common.h"
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#include <hal_log.h>
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#include <interrupt.h>
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#include <gpadc/platform_gpadc.h>
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#include <gpadc/common_gpadc.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* define this macro when debugging is required */
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/* #define CONFIG_DRIVERS_GPADC_DEBUG */
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#ifdef CONFIG_DRIVERS_GPADC_DEBUG
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#define GPADC_INFO(fmt, arg...) hal_log_info(fmt, ##arg)
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#else
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#define GPADC_INFO(fmt, arg...) do {}while(0)
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#endif
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#define GPADC_ERR(fmt, arg...) hal_log_err(fmt, ##arg)
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enum
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{
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GPADC_DOWN,
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GPADC_UP
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};
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typedef enum
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{
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GP_CH_0 = 0,
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GP_CH_1,
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GP_CH_2,
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GP_CH_3,
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GP_CH_4,
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GP_CH_5,
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GP_CH_6,
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GP_CH_7,
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GP_CH_8,
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GP_CH_9,
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GP_CH_A,
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GP_CH_B,
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GP_CH_C,
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GP_CH_D,
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GP_CH_E,
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GP_CH_MAX
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} hal_gpadc_channel_t;
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typedef enum
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{
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GPADC_IRQ_ERROR = -4,
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GPADC_CHANNEL_ERROR = -3,
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GPADC_CLK_ERROR = -2,
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GPADC_ERROR = -1,
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GPADC_OK = 0,
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} hal_gpadc_status_t;
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typedef enum gp_select_mode
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{
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GP_SINGLE_MODE = 0,
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GP_SINGLE_CYCLE_MODE,
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GP_CONTINUOUS_MODE,
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GP_BURST_MODE,
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} hal_gpadc_mode_t;
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typedef int (*gpadc_callback_t)(uint32_t data_type, uint32_t data);
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static uint32_t hal_gpadc_regs_offset[] = {
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GP_SR_REG,
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GP_CTRL_REG,
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GP_CS_EN_REG,
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GP_FIFO_INTC_REG,
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GP_FIFO_DATA_REG,
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GP_CB_DATA_REG,
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GP_DATAL_INTC_REG,
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GP_DATAH_INTC_REG,
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GP_DATA_INTC_REG,
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GP_CH0_CMP_DATA_REG,
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GP_CH1_CMP_DATA_REG,
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GP_CH2_CMP_DATA_REG,
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GP_CH3_CMP_DATA_REG,
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GP_CH4_CMP_DATA_REG,
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GP_CH5_CMP_DATA_REG,
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GP_CH6_CMP_DATA_REG,
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GP_CH7_CMP_DATA_REG,
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GP_CH8_CMP_DATA_REG,
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GP_CH9_CMP_DATA_REG,
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GP_CHA_CMP_DATA_REG,
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GP_CHB_CMP_DATA_REG,
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GP_CHC_CMP_DATA_REG,
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GP_CHD_CMP_DATA_REG,
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GP_CHE_CMP_DATA_REG,
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};
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typedef struct
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{
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uint32_t reg_base;
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uint32_t channel_num;
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uint32_t irq_num;
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uint32_t sample_rate;
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struct reset_control *reset;
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#if defined(CONFIG_SOC_SUN20IW1) || defined(CONFIG_ARCH_SUN8IW20) || defined(CONFIG_ARCH_SUN20IW2)
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hal_clk_id_t bus_clk;
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hal_clk_id_t rst_clk;
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hal_clk_t mbus_clk;
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hal_clk_t mbus_clk1;
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#else
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hal_clk_id_t mclk;
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hal_clk_id_t pclk;
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#endif
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hal_gpadc_mode_t mode;
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gpadc_callback_t callback[CHANNEL_MAX_NUM];
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uint32_t regs_backup[ARRAY_SIZE(hal_gpadc_regs_offset)];
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} hal_gpadc_t;
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int hal_gpadc_init(void);
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hal_gpadc_status_t hal_gpadc_deinit(void);
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hal_gpadc_status_t hal_gpadc_channel_init(hal_gpadc_channel_t channal);
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hal_gpadc_status_t hal_gpadc_channel_exit(hal_gpadc_channel_t channal);
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uint32_t gpadc_read_channel_data(hal_gpadc_channel_t channal);
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hal_gpadc_status_t hal_gpadc_register_callback(hal_gpadc_channel_t channal,
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gpadc_callback_t user_callback);
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void gpadc_key_enable_highirq(hal_gpadc_channel_t channal);
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void gpadc_key_disable_highirq(hal_gpadc_channel_t channal);
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#ifdef __cplusplus
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}
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#endif
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#endif
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