157 lines
6.4 KiB
C
Executable File
157 lines
6.4 KiB
C
Executable File
/**
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* @file hal_dcache.h
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* @author XRADIO IOT WLAN Team
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*/
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/*
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* Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DRIVER_CHIP_HAL_DCACHE_H_
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#define _DRIVER_CHIP_HAL_DCACHE_H_
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#include "sys/param.h"
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#include "driver/chip/hal_def.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define DCACHE_WT_ADDR_MAX 6
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typedef struct {
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__IO uint32_t START_ADDR; /* , Address offset: N * 0x4 + 0x00 */
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__IO uint32_t END_ADDR; /* , Address offset: N * 0x4 + 0x04 */
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__I uint32_t RESERVE08[2];
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} WRITE_THROUGH_ADDR_T;
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typedef struct {
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__IO uint32_t DCACHE_COM_CFG; /* , Address offset: 0x000 */
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__I uint32_t RESERVE04[3];
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WRITE_THROUGH_ADDR_T WT_ADDR[DCACHE_WT_ADDR_MAX]; /* , Address offset: 0x010 */
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__I uint32_t RESERVE40[8];
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__I uint32_t CBUS_WRITE_CNT; /* , Address offset: 0x090 */
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__I uint32_t CBUS_READ_CNT; /* , Address offset: 0x094 */
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__I uint32_t RESERVE98[2];
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__I uint32_t MISS_COUNT_H; /* , Address offset: 0x0A0 */
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__I uint32_t MISS_COUNT_L; /* , Address offset: 0x0A4 */
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__I uint32_t HIT_COUNT_H; /* , Address offset: 0x0A8 */
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__I uint32_t HIT_COUNT_L; /* , Address offset: 0x0AC */
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__I uint32_t DCACHE_STA; /* , Address offset: 0x0B0 */
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__I uint32_t RESERVEB4[3];
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__IO uint32_t CLEAN_FLUSH_SADDR; /* Address offset: 0x0C0, clean or flush start addr */
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__IO uint32_t CLEAN_FLUSH_LEN; /* Address offset: 0x0C4, clean or flush length */
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} DCACHE_T;
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#define DCACHE_CTRL ((DCACHE_T *)PSRAM_DCACHE_BASE)
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/* DCACHE_COM_CFG */
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#define DCACHE_ENABLE_SHIFT (0)
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#define DCACHE_ENABLE_MASK (0x1U << DCACHE_ENABLE_SHIFT)
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#define DCACHE_ASSOCIATE_MODE_SHIFT (3)
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#define DCACHE_ASSOCIATE_MODE_MASK (0x3U << DCACHE_ASSOCIATE_MODE_SHIFT)
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#define DCACHE_ASSOCIATE_DIRECT_MOD (0 << DCACHE_ASSOCIATE_MODE_SHIFT)
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#define DCACHE_ASSOCIATE_TWO_WAY_MOD (1 << DCACHE_ASSOCIATE_MODE_SHIFT)
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#define DCACHE_ASSOCIATE_FOUR_WAY_MOD (2 << DCACHE_ASSOCIATE_MODE_SHIFT)
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#define DCACHE_EN_VICTIM_SHIFT (5)
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#define DCACHE_EN_VICTIM_MASK (0x1U << DCACHE_EN_VICTIM_SHIFT)
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#define DCACHE_EN_VICTIM (0x1U << DCACHE_EN_VICTIM_SHIFT)
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#define DCACHE_EN_RD_WRAP_SHIFT (6)
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#define DCACHE_EN_RD_WRAP_MASK (0x1U << DCACHE_EN_RD_WRAP_SHIFT)
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#define DCACHE_EN_RD_WRAP (0x1U << DCACHE_EN_RD_WRAP_SHIFT)
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#define DCACHE_COUNTER_EN_SHIFT (7)
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#define DCACHE_COUNTER_EN_MASK (0x1U << DCACHE_COUNTER_EN_SHIFT)
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#define DCACHE_CLEAN_START_SHIFT (8)
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#define DCACHE_CLEAN_START_MASK (0x1U << DCACHE_CLEAN_START_SHIFT)
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#define DCACHE_FLUSH_START_SHIFT (9)
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#define DCACHE_FLUSH_START_MASK (0x1U << DCACHE_FLUSH_START_SHIFT)
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#define DCACHE_FLUSH_CLEAN_START_SHIFT (10)
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#define DCACHE_FLUSH_CLEAN_START_MASK (0x1U << DCACHE_FLUSH_CLEAN_START_SHIFT)
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#if (CONFIG_CHIP_ARCH_VER == 2)
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#define DCACHE_MIXED_IDBUS_EN_SHIFT (11)
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#define DCACHE_MIXED_IDBUS_EN (0x1U << DCACHE_MIXED_IDBUS_EN_SHIFT)
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#define DCACHE_MIXED_MODE_IDSHIFT (12)
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#define DCACHE_MIXED_MODE_ICACHE (0x0U << DCACHE_MIXED_MODE_IDSHIFT)
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#define DCACHE_MIXED_MODE_DCACHE (0x1U << DCACHE_MIXED_MODE_IDSHIFT)
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#define DCACHE_MIXED_MODE_SHIFT (DCACHE_MIXED_IDBUS_EN_SHIFT)
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typedef enum {
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DCACHE_MIXED_MODE_ID = 0 << DCACHE_MIXED_MODE_SHIFT, /* both use ICache cache Instruction, use DCache cache Data */
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DCACHE_MIXED_MODE_I = 1 << DCACHE_MIXED_MODE_SHIFT, /* only use ICache cache Instruction */
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DCACHE_MIXED_MODE_D = 3 << DCACHE_MIXED_MODE_SHIFT, /* only use DCache cache Instruction and Data */
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} DCACHE_MIXED_MODE;
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#endif /* CONFIG_CHIP_ARCH_VER == 2 */
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#define DCACHE_ASSOCIATE_MODE_DIRECT 0
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#define DCACHE_ASSOCIATE_MODE_TWO_WAY 1
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#define DCACHE_ASSOCIATE_MODE_FOUR_WAY 2
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typedef struct {
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uint8_t way_mode;
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uint8_t vc_en;
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uint8_t wrap_en;
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#if (CONFIG_CHIP_ARCH_VER == 2)
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uint32_t mixed_mode;
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#endif
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} DCache_Config;
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int32_t HAL_Dcache_Request_WriteThroughIndex(void);
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int32_t HAL_Dcache_Release_WriteThroughIndex(int32_t index);
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int32_t HAL_Dcache_Config_WriteThrough(int32_t index, uint32_t sadd, uint32_t eadd);
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/* only addr >= PSRAM_START_ADDR and addr + len <= PSRAM_END_ADDR and
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* [addr, addr + len) not in any of write through area, will return 1.
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* otherwise reutn 0.
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*/
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int32_t HAL_Dcache_IsCacheable(uint32_t addr, uint32_t len);
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int32_t HAL_Dcache_IsPSramCacheable(uint32_t addr, uint32_t len);
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void HAL_Dcache_FlushAll(void);
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void HAL_Dcache_Clean(uint32_t sadd, uint32_t len);
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void HAL_Dcache_CleanAll(void);
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void HAL_Dcache_Flush(uint32_t sadd, uint32_t len);
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void HAL_Dcache_DumpMissHit(void);
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void HAL_Dcache_DumpCbusCnt(void);
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void HAL_Dcache_Init(DCache_Config *cfg);
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void HAL_Dcache_DeInit(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _DRIVER_CHIP_HAL_DCACHE_H_ */
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