289 lines
12 KiB
C
Executable File
289 lines
12 KiB
C
Executable File
/**
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* @file hal_i2c.h
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* @author XRADIO IOT WLAN Team
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*/
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/*
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* Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DRIVER_CHIP_HAL_I2C_H_
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#define _DRIVER_CHIP_HAL_I2C_H_
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#include "driver/chip/hal_def.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief I2C ID definition
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*/
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typedef enum {
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I2C0_ID = 0,
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I2C1_ID = 1,
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I2C_NUM = 2
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} I2C_ID;
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/**
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* @brief I2C register block structure
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*/
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typedef struct {
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__IO uint32_t I2C_ADDR; /* offset: 0x00, I2C slave address register */
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__IO uint32_t I2C_XADDR; /* offset: 0x04, I2C extend slave address register */
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__IO uint32_t I2C_DATA; /* offset: 0x08, I2C data register */
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__IO uint32_t I2C_CTRL; /* offset: 0x0C, I2C control register */
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__I uint32_t I2C_STATUS; /* offset: 0x10, I2C status register */
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__IO uint32_t I2C_CLK_CTRL; /* offset: 0x14, I2C clock register */
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__IO uint32_t I2C_SOFT_RST; /* offset: 0x18, I2C software reset register */
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__IO uint32_t I2C_EFR; /* offset: 0x1C, I2C enhance feature register */
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__IO uint32_t I2C_LINE_CTRL; /* offset: 0x20, I2C line control register */
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} I2C_T;
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#define I2C0 ((I2C_T *)I2C0_BASE) /* address: 0x40041C00 */
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#define I2C1 ((I2C_T *)I2C1_BASE) /* address: 0x40042000 */
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/* I2Cx->I2C_ADDR, R/W */
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#define I2C_SLAVE_ADDR_SHIFT 1
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#define I2C_SLAVE_ADDR_MASK (0x7FU << I2C_SLAVE_ADDR_SHIFT)
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#define I2C_GCE_BIT HAL_BIT(0)
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/* I2Cx->I2C_XADDR, R/W */
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#define I2C_SLAVE_XADDR_MASK 0xFFU
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/* I2Cx->I2C_DATA, R/W */
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#define I2C_DATA_MASK 0xFFU
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/* I2Cx->I2C_CTRL, R/W */
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#define I2C_IRQ_EN_BIT HAL_BIT(7)
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#define I2C_BUS_EN_BIT HAL_BIT(6)
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#define I2C_START_BIT HAL_BIT(5)
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#define I2C_STOP_BIT HAL_BIT(4)
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#define I2C_IRQ_FLAG_BIT HAL_BIT(3)
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#define I2C_ACK_EN_BIT HAL_BIT(2)
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#define I2C_WR_CTRL_MASK (I2C_START_BIT | I2C_STOP_BIT | I2C_IRQ_FLAG_BIT)
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/* I2Cx->I2C_STATUS, R */
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#define I2C_STATUS_MASK 0xFFU
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typedef enum {
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I2C_BUS_ERROR = 0x00U, /* bus error */
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I2C_START_TRAN = 0x08U, /* start condition transmitted */
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I2C_RE_START_TRAN = 0x10U, /* repeated start condition transmitted */
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I2C_ADDR_WR_TRAN_ACK = 0x18U, /* address + write bit transmitted, ACK received */
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I2C_ADDR_WR_TRAN_NACK = 0x20U, /* address + write bit transmitted, ACK not received */
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I2C_MASTER_DATA_TRAN_ACK = 0x28U, /* data byte transmitted in master mode, ACK received */
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I2C_MASTER_DATA_TRAN_NACK = 0x30U, /* data byte transmitted in master mode, ACK not received */
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I2C_ARB_LOST = 0x38U, /* arbitration lost in address or data byte */
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I2C_ADDR_RD_TRAN_ACK = 0x40U, /* address + read bit transmitted, ACK received */
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I2C_ADDR_RD_TRAN_NACK = 0x48U, /* address + read bit transmitted, ACK not received */
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I2C_MASTER_DATA_RECV_ACK = 0x50U, /* data byte received in master mode, ACK transmitted */
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I2C_MASTER_DATA_RECV_NACK = 0x58U, /* data byte received in master mode, ACK not transmitted */
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I2C_ADDR_WR_RECV_ACK = 0x60U, /* slave address + write bit received, ACK transmitted */
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I2C_ARB_LOST_ADDR_WR = 0x68U, /* arbitration lost in address as master, slave address + write bit received, ACK transmitted */
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I2C_GC_ADDR_RECV = 0x70U, /* general call adress received, ACK transmitted */
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I2C_ARB_LOST_GC_ADDR = 0x78U, /* arbitration lost in address as master, general call address received, ACK transmitted */
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I2C_DATA_RECV_SLAVE_ACK = 0x80U, /* data byte received after slave address received, ACK transmitted */
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I2C_DATA_RECV_SLAVE_NACK = 0x88U, /* data byte reveived after slave address received, ACK not transmitted */
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I2C_DATA_RECV_GC_ACK = 0x90U, /* data byte received after general call received, ACK transmitted */
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I2C_DATA_RECV_GC_NACK = 0x98U, /* data byte received after general call received, ACK not transmitted */
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I2C_STOP_RE_START_RECV = 0xA0U, /* stop or repeated start condition received in slave mode */
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I2C_ADDR_RD_RECV_ACK = 0xA8U, /* slave address + read bit received, ACK transmitted */
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I2C_ARB_LOST_ADDR_RD = 0xB0U, /* arbitration lost in address as master, slave address + read bit received, ACK transmitted */
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I2C_SLAVE_DATA_TRAN_ACK = 0xB8U, /* data byte transmitted in slave mode, ACK received */
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I2C_SLAVE_DATA_TRAN_NACK = 0xC0U, /* data byte transmitted in slave mode, ACK not received */
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I2C_SLAVE_LAST_TRAN_ACK = 0xC8U, /* last byte transmitted in slave mode, ACK received */
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I2C_SEC_ADDR_WR_ACK = 0xD0U, /* second address byte + write bit transmitted, ACK received */
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I2C_SEC_ADDR_WR_NACK = 0xD8U, /* second address byte + write bit transmitted, ACK not received */
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I2C_NO_STATUS_INFO = 0xF8U /* no relevant status information, IRQ_FLAG = 0 */
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} I2C_IRQStatus;
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/* I2Cx->I2C_CLK_CTRL, R/W */
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#define I2C_CLK_M_SHIFT 3
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#define I2C_CLK_M_MASK (0xFU << I2C_CLK_M_SHIFT)
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#define I2C_CLK_M_MAX 15
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#define I2C_CLK_N_SHIFT 0
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#define I2C_CLK_N_MASK (0x7U << I2C_CLK_N_SHIFT)
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#define I2C_CLK_N_MAX 7
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/* I2Cx->I2C_SOFT_RST, R/W */
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#define I2C_SOFT_RST_BIT HAL_BIT(0)
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/* I2Cx->I2C_EFR, R/W */
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#define I2C_DATA_BYTE_MASK 0x3U
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typedef enum {
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I2C_DATA_BYTE_0 = 0U,
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I2C_DATA_BYTE_1 = 1U,
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I2C_DATA_BYTE_2 = 2U,
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I2C_DATA_BYTE_3 = 3U
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} I2C_DataByte;
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/* I2Cx->I2C_LINE_CTRL, R/W */
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#define I2C_SCL_STATE_BIT HAL_BIT(5)
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#define I2C_SDA_STATE_BIT HAL_BIT(4)
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#define I2C_SCL_CTRL_BIT HAL_BIT(3)
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#define I2C_SCL_CTRL_EN_BIT HAL_BIT(2)
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#define I2C_SDA_CTRL_BIT HAL_BIT(1)
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#define I2C_SDA_CTRL_EN_BIT HAL_BIT(0)
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#define I2C_LINE_STATE_MASK (I2C_SCL_STATE_BIT | I2C_SDA_STATE_BIT)
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#define I2C_LINE_CTRL_MASK (I2C_SCL_CTRL_EN_BIT | I2C_SDA_CTRL_EN_BIT)
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#define I2C_LINE_CTRL_LEVEL_MASK (I2C_SCL_CTRL_BIT | I2C_SDA_CTRL_BIT)
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/******************************************************************************/
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/**
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* @brief I2C addressing mode
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*/
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typedef enum {
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I2C_ADDR_MODE_7BIT = 0U, /* 7-bit addressing mode */
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I2C_ADDR_MODE_10BIT = 1U /* 10-bit addressing mode */
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} I2C_AddrMode;
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/**
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* @brief I2C memmory address size definition
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*/
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typedef enum {
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I2C_MEMADDR_SIZE_INVALID = 0,
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I2C_MEMADDR_SIZE_8BIT = 1,
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I2C_MEMADDR_SIZE_16BIT = 2,
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I2C_MEMADDR_SIZE_32BIT = 4,
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} I2C_MemAddrSize;
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/**
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* @brief I2C initialization parameters
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*/
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typedef struct {
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I2C_AddrMode addrMode; /* addressing mode */
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uint32_t clockFreq; /* clock frequency */
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} I2C_InitParam;
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/**
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* @brief Initialize the I2C according to the specified parameters
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* @param[in] i2cID ID of the specified I2C
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* @param[in] initParam Pointer to I2C_InitParam structure
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* @retval HAL_Status, HAL_OK on success
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*/
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HAL_Status HAL_I2C_Init(I2C_ID i2cID, const I2C_InitParam *initParam);
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/**
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* @brief DeInitialize the specified I2C
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* @param[in] i2cID ID of the specified I2C
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* @retval HAL_Status, HAL_OK on success
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*/
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HAL_Status HAL_I2C_DeInit(I2C_ID i2cID);
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/**
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* @brief Transmit an amount of data in interrupt mode
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* @param[in] i2cID ID of the specified I2C
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* @param[in] devAddr Device address
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* @param[in] buf Pointer to the data buffer
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* @param[in] size Number of bytes to be transmitted
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* @return Number of bytes transmitted, -1 on error
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*/
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int32_t HAL_I2C_Master_Transmit_IT(I2C_ID i2cID, uint16_t devAddr, uint8_t *buf, int32_t size);
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/**
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* @brief Receive an amount of data in interrupt mode
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* @param[in] i2cID ID of the specified I2C
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* @param[in] devAddr Device address
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* @param[in] buf Pointer to the data buffer
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* @param[in] size Number of bytes to be received
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* @return Number of bytes received, -1 on error
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*/
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int32_t HAL_I2C_Master_Receive_IT(I2C_ID i2cID, uint16_t devAddr, uint8_t *buf, int32_t size);
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/**
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* @brief Transmit an amount of data to specified memory or register of the
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* slave device in interrupt mode
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* @param[in] i2cID ID of the specified I2C
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* @param[in] devAddr Device address
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* @param[in] memAddr Memory or register address
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* @param[in] memAddrSize Memory address size
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* @param[in] buf Pointer to the data buffer
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* @param[in] size Number of bytes to be transmitted
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* @return Number of bytes transmitted, -1 on error
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*/
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int32_t HAL_I2C_Master_Transmit_Mem_IT(I2C_ID i2cID, uint16_t devAddr, uint32_t memAddr, I2C_MemAddrSize memAddrSize, uint8_t *buf, int32_t size);
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/**
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* @brief Receive an amount of data from specified memory or register of the
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* slave device in interrupt mode
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* @param[in] i2cID ID of the specified I2C
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* @param[in] devAddr Device address
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* @param[in] memAddr Memory or register address
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* @param[in] memAddrSize Memory address size
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* @param[in] buf Pointer to the data buffer
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* @param[in] size Number of bytes to be received
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* @return Number of bytes received, -1 on error
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*/
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int32_t HAL_I2C_Master_Receive_Mem_IT(I2C_ID i2cID, uint16_t devAddr, uint32_t memAddr, I2C_MemAddrSize memAddrSize, uint8_t *buf, int32_t size);
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/**
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* @brief Transmit one byte data through SCCB protocol in interrupt mode
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* @param[in] i2cID ID of the specified I2C
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* @param[in] devAddr Device address
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* @param[in] subAddr Sub-address
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* @param[in] buf Pointer to the data buffer
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* @return Number of bytes transmitted, -1 on error
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*/
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int32_t HAL_I2C_SCCB_Master_Transmit_IT(I2C_ID i2cID, uint8_t devAddr, uint8_t subAddr, uint8_t *buf);
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/**
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* @brief Receive one byte data through SCCB protocol in interrupt mode
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* @param[in] i2cID ID of the specified I2C
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* @param[in] devAddr Device address
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* @param[in] subAddr Sub-address
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* @param[in] buf Pointer to the data buffer
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* @return Number of bytes received, -1 on error
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*/
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int32_t HAL_I2C_SCCB_Master_Receive_IT(I2C_ID i2cID, uint8_t devAddr, uint8_t subAddr, uint8_t *buf);
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/**
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* @brief Reset the specified I2C
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* @param[in] i2cID ID of the specified I2C
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* @retval void
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*/
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void HAL_I2C_Reset(I2C_ID i2cID);
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/**
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* @brief Reset the bus, when bus busy
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* @param[in] i2cID ID of the specified I2C
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* @retval void
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*/
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void HAL_I2C_Busy_Reset(I2C_ID i2cID);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _DRIVER_CHIP_HAL_I2C_H_ */
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