158 lines
6.3 KiB
C
Executable File
158 lines
6.3 KiB
C
Executable File
/**
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* @file hal_icache.h
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* @author XRADIO IOT WLAN Team
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*/
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/*
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* Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DRIVER_CHIP_HAL_ICACHE_H_
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#define _DRIVER_CHIP_HAL_ICACHE_H_
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#include <stdbool.h>
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#include "sys/param.h"
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#include "driver/chip/hal_def.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if (CONFIG_CHIP_ARCH_VER == 2)
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typedef struct {
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uint32_t way_mode;
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uint8_t vc_en;
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uint8_t wrap_en;
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uint8_t bypass;
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} ICache_Config;
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typedef struct {
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/*uint32_t prefetch_cache_size;*/ /* in bytes, recommended size is no more than ICache_Config.cache_size */
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bool prefetch_2nd_branch;
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uint32_t addr_prefetch_start;
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} ICache_PrefetchConfig;
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typedef enum {
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FLASH_CACHE_PREFETCH_ENABLE = 0,
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FLASH_CACHE_PREFETCH_DISABLE = 1
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} Flash_Cache_Prefetch;
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typedef struct {
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struct {
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uint32_t addr_interrupt_vector;
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uint32_t addr_interrupt_cb;
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} prefetch_interrupt[16];
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} FlashCache_PrefetchIntConfig;
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typedef struct {
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__IO uint32_t CACHE_COM_CFG; /* , Address offset: 0x000 */
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__IO uint32_t RESERVE4[39];
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__I uint32_t MISS_COUNT_H; /* , Address offset: 0x0A0 */
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__I uint32_t MISS_COUNT_L; /* , Address offset: 0x0A4 */
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__I uint32_t HIT_COUNT_H; /* , Address offset: 0x0A8 */
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__I uint32_t HIT_COUNT_L; /* , Address offset: 0x0AC */
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__I uint32_t CACHE_STA; /* , Address offset: 0x0B0 */
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__I uint32_t INSTR_WAIT_H; /* , Address offset: 0x0B4 */
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__I uint32_t INSTR_WAIT_L; /* , Address offset: 0x0B8 */
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} ICACHE_T;
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#define ICACHE_CTRL ((ICACHE_T *)FLASH_CACHE_BASE)
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/* I-cache Common Configuration */
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#define ICACHE_ENABLE_SHIFT 0
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#define ICACHE_ENABLE_MASK (0x1U << ICACHE_ENABLE_SHIFT)
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#define ICACHE_ASSOCIATE_MODE_SHIFT 3
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#define ICACHE_ASSOCIATE_MODE_MASK (0x3U << ICACHE_ASSOCIATE_MODE_SHIFT)
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enum ICACHE_ASSO_MOD {
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ICACHE_ASSO_MOD_DIR = (0 << ICACHE_ASSOCIATE_MODE_SHIFT),
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ICACHE_ASSO_MOD_2W = (1 << ICACHE_ASSOCIATE_MODE_SHIFT),
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ICACHE_ASSO_MOD_4W = (2 << ICACHE_ASSOCIATE_MODE_SHIFT),
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};
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#define ICACHE_FLUSH_ALL_SHIFT 5
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#define ICACHE_FLUSH_ALL_MASK (0x1U << ICACHE_FLUSH_ALL_SHIFT)
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#define ICACHE_EN_VICTIM_CACHE_SHIFT 6
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#define ICACHE_EN_VICTIM_CACHE_MASK (0x1U << ICACHE_EN_VICTIM_CACHE_SHIFT)
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#define ICACHE_EN_ICACHE_WRAP_SHIFT 7
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#define ICACHE_EN_ICACHE_WRAP_MASK (0x1U << ICACHE_EN_ICACHE_WRAP_SHIFT)
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#define ICACHE_COUNTER_EN_SHIFT 8
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#define ICACHE_COUNTER_EN_MASK (0x1U << ICACHE_COUNTER_EN_SHIFT)
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#define ICACHE_CBUS_HREADY_TIMEOUT_EN_SHIFT 9
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#define ICACHE_CBUS_HREADY_TIMEOUT_EN_MASK (0x1U << ICACHE_CBUS_HREADY_TIMEOUT_EN_SHIFT)
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#define ICACHE_CBUS_HREADY_WAIT_TIMEOUT_SHIFT 10
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#define ICACHE_CBUS_HREADY_WAIT_TIMEOUT_MASK (0xFFU << ICACHE_CBUS_HREADY_WAIT_TIMEOUT_SHIFT)
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/* Miss Count Status H-Register */
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#define ICACHE_MISS_COUNT_H_SHIFT 0
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#define ICACHE_MISS_COUNT_H_MASK (0xFFFFU << ICACHE_MISS_COUNT_H_SHIFT)
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/* Miss Count Status L-Register */
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#define ICACHE_MISS_COUNT_L_SHIFT 0
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#define ICACHE_MISS_COUNT_L_MASK (0xFFFFU << ICACHE_MISS_COUNT_L_SHIFT)
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/* Hit Count Status H-Register */
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#define ICACHE_HIT_COUNT_H_SHIFT 0
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#define ICACHE_HIT_COUNT_H_MASK (0xFFFFFFFFU << ICACHE_HIT_COUNT_H_SHIFT)
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/* Hit Count Status L-Register */
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#define ICACHE_HIT_COUNT_L_SHIFT 0
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#define ICACHE_HIT_COUNT_L_MASK (0xFFFFFFFFU << ICACHE_HIT_COUNT_L_SHIFT)
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/* Cache State Register */
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#define ICACHE_CACHE_STATE_SHIFT 0
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#define ICACHE_CACHE_STATE_MASK (0x7U << ICACHE_CACHE_STATE_SHIFT)
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/* Instruction Wait Cycle H-Register */
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#define ICACHE_INSTR_WAIT_H_SHIFT 0
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#define ICACHE_INSTR_WAIT_H_MASK (0xFFFFFFFFU << ICACHE_INSTR_WAIT_H_SHIFT)
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/* Instruction Wait Cycle L-Register */
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#define ICACHE_INSTR_WAIT_L_SHIFT 0
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#define ICACHE_INSTR_WAIT_L_MASK (0xFFFFFFFFU << ICACHE_INSTR_WAIT_L_SHIFT)
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#define ICACHE_ASSOCIATE_MODE_DIRECT 0
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#define ICACHE_ASSOCIATE_MODE_TWO_WAY 1
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#define ICACHE_ASSOCIATE_MODE_FOUR_WAY 2
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void HAL_ICache_Flush(void);
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HAL_Status HAL_ICache_Config(ICache_Config *cfg);
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HAL_Status HAL_ICache_DeConfig(void);
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HAL_Status HAL_ICache_Init(ICache_Config *cfg);
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HAL_Status HAL_ICache_Deinit(void);
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HAL_Status HAL_ICache_EnablePrefetch(ICache_PrefetchConfig *cfg);
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HAL_Status HAL_ICache_DisablePrefetch(void);
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#endif /* CONFIG_CHIP_ARCH_VER */
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#ifdef __cplusplus
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}
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#endif
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#endif /* _DRIVER_CHIP_HAL_ICACHE_H_ */
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