411 lines
14 KiB
C
Executable File
411 lines
14 KiB
C
Executable File
/**
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* @file hal_pwm.h
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* @author XRADIO IOT WLAN Team
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*/
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/*
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* Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DRIVER_CHIP_HAL_PWM_H_
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#define _DRIVER_CHIP_HAL_PWM_H_
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#include "driver/chip/hal_def.h"
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#include "driver/chip/hal_gpio.h"
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#include "driver/chip/hal_clock.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief PWM group id.
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*/
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typedef enum {
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PWM_GROUP_0, /*!<PWM GROUP 0, include channel_0 and channel_1*/
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PWM_GROUP_1, /*!<PWM GROUP 1, include channel_2 and channel_3*/
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PWM_GROUP_2, /*!<PWM GROUP 2, include channel_4 and channel_5*/
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PWM_GROUP_3, /*!<PWM GROUP 3, include channel_6 and channel_7*/
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PWM_GROUP_NUM,
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PWM_GROUP_NULL = PWM_GROUP_NUM,
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} PWM_GROUP_ID;
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/**
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* @brief PWM channel id.
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*/
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typedef enum {
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PWM_GROUP0_CH0 = 0U, /*!< bit 0 PORTA_PIN8 or PORTA_PIN19 */
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PWM_GROUP0_CH1 = 1U, /*!< bit 1 PORTA_PIN9 or PORTA_PIN20 */
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PWM_GROUP1_CH2 = 2U, /*!< bit 2 PORTA_PIN10 or PORTA_PIN21 */
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PWM_GROUP1_CH3 = 3U, /*!< bit 3 PORTA_PIN11 or PORTA_PIN22 */
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PWM_GROUP2_CH4 = 4U, /*!< bit 4 PORTA_PIN12 or PORTB_PIN0 */
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PWM_GROUP2_CH5 = 5U, /*!< bit 5 PORTA_PIN13 or PORTB_PIN1 */
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PWM_GROUP3_CH6 = 6U, /*!< bit 6 PORTA_PIN14 or PORTB_PIN2 */
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PWM_GROUP3_CH7 = 7U, /*!< bit 7 PORTA_PIN15 or PORTB_PIN3 */
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PWM_CH_NUM = 8U,
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PWM_CH_NULL = PWM_CH_NUM,
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} PWM_CH_ID;
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/**
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* @brief The register for PWM.
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*/
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typedef struct {
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__IO uint32_t PCR; /*!< PWM Control Register, Address offset: 0x60+0x0+N*0X20(N=0~7) */
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__IO uint32_t PPR; /*!< PWM Period Register, Address offset: 0x60+0x4+N*0X20(N=0~7) */
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__I uint32_t PCNTR; /*!< PWM Count Register, Address offset: 0x60+0x8+N*0X20(N=0~7) */
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__IO uint32_t CCR; /*!< Capture Control Register, Address offset: 0x60+0xC+N*0X20(N=0~7) */
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__IO uint32_t CRLR; /*!< Capture Rise Lock Register, Address offset: 0x60+0x10+N*0X20(N=0~7) */
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__IO uint32_t CFLR; /*!< Capture Fall Lock Register, Address offset: 0x60+0x14+N*0X20(N=0~7) */
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uint32_t RESERVED0[2];
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} PWM_CHANNEL_REG;
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/**
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* @brief The register for PWM.
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*/
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typedef struct {
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__IO uint32_t PIER; /*!< PWM IRQ Enable Register, Address offset: 0x00 */
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__IO uint32_t PISR; /*!< PWM IRQ Status Register, Address offset: 0x04 */
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uint32_t RESERVED0[2]; /*!< NULL*/
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__IO uint32_t CIER; /*!< Capture IRQ Enable Register, Address offset: 0x10 */
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__IO uint32_t CISR; /*!< Capture IRQ Status Register, Address offset: 0x14 */
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uint32_t RESERVED1[2]; /*!< NULL*/
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__IO uint32_t PCCR[4]; /*!< PWM01 Clock Configuration Register Address offset: 0x20 */
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__IO uint32_t PDZCR[4]; /*!< PWM01 Dead Zone Control Register, Address offset: 0x30 */
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__IO uint32_t PER; /*!< PWM Enable Register, Address offset: 0x40 */
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__IO uint32_t CER; /*!< PWM Capture Enable Register, Address offset: 0x44 */
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uint32_t RESERVED2[6];
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PWM_CHANNEL_REG CH_REG[PWM_CH_NUM];
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} PWM_T;
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#define PWM ((PWM_T *)PWM_BASE)
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/**
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* @brief The clock division for PWM group.
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*/
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typedef enum {
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PWM_SRC_CLK_DIV_1 = 0U, /*!< Src Clk Frequency division 1 */
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PWM_SRC_CLK_DIV_2 = 1U, /*!< Src Clk Frequency division 2 */
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PWM_SRC_CLK_DIV_4 = 2U, /*!< Src Clk Frequency division 4 */
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PWM_SRC_CLK_DIV_8 = 3U, /*!< Src Clk Frequency division 8 */
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PWM_SRC_CLK_DIV_16 = 4U, /*!< Src Clk Frequency division 16 */
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PWM_SRC_CLK_DIV_32 = 5U, /*!< Src Clk Frequency division 32 */
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PWM_SRC_CLK_DIV_64 = 6U, /*!< Src Clk Frequency division 64 */
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PWM_SRC_CLK_DIV_128 = 7U, /*!< Src Clk Frequency division 128 */
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PWM_SRC_CLK_DIV_256 = 8U, /*!< Src Clk Frequency division 256 */
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} PWM_SrcClkDiv;
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#define PWM_SRC_CLK_DIV_V ((uint32_t)0x0000000F)
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#define PWM_CH_CLK_GATING HAL_BIT(4)
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#define PWM_LOW_CH_CLKBYPASS HAL_BIT(5)
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#define PWM_HIGH_CH_CLKBYPASS HAL_BIT(6)
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#define PWM_SRC_CLK_SELECT ((uint32_t)0x00000180) /* bit8 ignore, 01:APB1 00:24M */
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/* Bit definition for PWMxx(G01,G23,G45,G67) Dead Zone Control register **************/
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#define PWM_CH_DZ_EN HAL_BIT(0)
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#define PWM_CH_DZ_INV ((uint32_t)0x0000FF00) /* PWM Dead Zone interval value */
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/******************** Bit definition for PWM Control register **********************/
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#define PWM_PCR_PRESCAL ((uint32_t)0x000000FF)
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#define PWM_PCR_ACT_STA HAL_BIT(8)
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#define PWM_PCR_MODE HAL_BIT(9)
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#define PWM_PCR_PLUSE_START HAL_BIT(10)
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#define PWM_PCR_PERIODRDY HAL_BIT(11)
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/*************** Bit definition for PWM Period register ****************************/
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#define PWM_PPR_ACT_CYCLE ((uint32_t)0x0000FFFF)
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#define PWM_PPR_ENTIER_CYCLE ((uint32_t)0xFFFF0000)
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/*************** Bit definition for PWM Counter register ***************************/
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#define PWM_TIME_COUNTER ((uint32_t)0x0000FFFF)
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/*************** Bit definition for Capture Control register ***********************/
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#define PWM_CCR_CAPINV HAL_BIT(0)
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#define PWM_CCR_CFLF HAL_BIT(1)
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#define PWM_CCR_CRLF HAL_BIT(2)
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/*************** Bit definition for Capture Rise Lock register *********************/
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#define PWM_CRLR ((uint32_t)0x0000FFFF)
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/*************** Bit definition for Capture Fall Lock register **********************/
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#define PWM_CFLR ((uint32_t)0x0000FFFF)
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/*************** Bit definition for PWM Enable register *****************************/
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/**
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* @brief The sorce clock for PWM group.
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*/
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typedef enum {
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PWM_CLK_HOSC,
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PWM_CLK_APB1,
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} PWM_GroupSrcClk;
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/**
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* @brief The run mode for PWM channel.
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*/
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typedef enum {
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PWM_CYCLE_MODE, /*!< The ouput signal is cycle */
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PWM_PLUSE_MODE, /*!< Run in this mode, caller HAL_PWM_PluseStart(PWM_CH_ID ch_id) produce one pluse */
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PWM_CAPTURE_MODE, /*!< Capture the input signal */
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} PWM_Mode;
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/**
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* @brief The Polarity for PWM channel.
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*/
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typedef enum {
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PWM_LOWLEVE,
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PWM_HIGHLEVE,
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} PWM_Polarity;
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/**
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* @brief The PWM interrupt event.
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*/
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typedef enum {
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PWM_IRQ_OUTPUT,
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PWM_IRQ_RISEEDGE,
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PWM_IRQ_FALLEDGE,
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PWM_IRQ_BOTHEDGE,
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PWM_IRQ_NULL,
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} PWM_IrqEvent;
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/**
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* @brief The PWM interrupt callback.
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* @param arg: The param for callback.
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* @param event: The interrupt event.
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*/
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typedef void (*PWM_IrqCallback) (void *arg, PWM_IrqEvent event);
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/**
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* @brief Config PWM interrupt.
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*/
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typedef struct {
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PWM_IrqEvent event; /*!< The interrupt event */
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PWM_IrqCallback callback; /*!< The interrupt callback */
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void *arg; /*!< The callback param */
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} PWM_IrqParam;
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/**
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* @brief Config PWM group clock.
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*/
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typedef struct {
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PWM_GroupSrcClk clk; /*!< The source clock for PWM group */
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PWM_SrcClkDiv div; /*!< The division for clock */
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} PWM_ClkParam;
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/**
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* @brief Config PWM channel.
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*/
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typedef struct {
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PWM_Mode mode; /*!< The channel's run mode */
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PWM_Polarity polarity; /*!< The channel's polarity */
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uint32_t hz; /*!< The channel's output requncy ; run in capture mode , it's intput signal's requency */
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} PWM_ChInitParam;
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/**
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* @brief Config PWM Complementary.
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*/
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typedef struct {
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PWM_Polarity polarity; /*!< The channel's polarity, used for number of small channels, another
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channel's polarity is opposite */
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uint32_t hz; /*!< The channel's output equncy */
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} PWM_CompInitParam;
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/**
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* @brief Save capture result.
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*/
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typedef struct {
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uint32_t highLevelTime;
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uint32_t lowLevelTime;
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uint32_t periodTime;
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} PWM_CapResult;
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/**
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* @brief Capture mode.
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*/
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typedef enum {
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PWM_CAP_PLUSE, /*!< Used for capture pluse */
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PWM_CAP_CYCLE, /*!< Used for capture continuous signal */
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} PWM_CaptureMode;
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/**
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* @brief Configure the pwm group source clock.
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* @note This function is used to configure the group source clock ,
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* each group contains two channels.
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* For example : The group_0's clock is effect channel0 and channel 1.
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* @param group_id: The pwm group id.
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* @param param:
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* @arg param->clk:The source clk of this group.
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* @arg param->div:The division for source clk.
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* @retval HAL_Status: The status of driver
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*/
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HAL_Status HAL_PWM_GroupClkCfg(PWM_GROUP_ID group_id, PWM_ClkParam *param);
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/**
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* @brief Init the pwm channel.
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* @note This function is used to configure the channel pin(IO mode), output frequency ,
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* polarity and rum mode.
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* @param ch_id: The pwm channel id.
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* @param param:
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* @arg param->mode:The channels run mode.
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* @arg param->polarity:The channels polarity.
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* @arg param->hz:The channels output frequency.
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* @retval max_duty_ratio: The channel max duty cycle value. if the mode is
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* capture, the return value is 0. error return -1;
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*/
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int HAL_PWM_ChInit(PWM_CH_ID ch_id, PWM_ChInitParam *param);
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/**
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* @brief Deinit the pwm channel.
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* @note This function is used to deinit the channel pin, reduce power consumption.
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* @param ch_id: The pwm channel id.
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* @retval HAL_Status: The status of driver.
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*/
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HAL_Status HAL_PWM_ChDeinit(PWM_CH_ID ch_id);
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/**
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* @brief Init the complementary mode.
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* @note This function is used to configure the groups pin(IO mode), output frequency ,
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* polarity.
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* This mode is two channel output complementart waveform, the channel run in
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* cycle mode.
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* @param group_id: The pwm group id.
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* @param param:
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* @arg param->polarity:The channels polarity.
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* @arg param->hz:The channels output frequency.
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* @retval HAL_Status: The channel max duty cycle value.
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*/
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int HAL_PWM_ComplementaryInit(PWM_GROUP_ID group_id, PWM_CompInitParam *param);
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/**
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* @brief Deinit the pwm complementary.
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* @note This function is used to deinit the groupl pin, reduce power consumption.
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* @param group_id: The pwm group id.
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* @retval HAL_Status: The status of driver.
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*/
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HAL_Status HAL_PWM_ComplementaryDeInit(PWM_GROUP_ID group_id);
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/**
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* @brief Enable the pwm channel.
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* @param ch_id: The pwm channel id.
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* @param mode: The pwm channel run mode.
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* @param en: set 1 enable , 0 disable.
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* @retval HAL_Status: The status of driver.
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*/
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HAL_Status HAL_PWM_EnableCh(PWM_CH_ID ch_id, PWM_Mode mode, uint8_t en);
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/**
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* @brief Output one pluse.Use this function you need already enable the channel.
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* @param ch_id: The pwm channel id.
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* @retval HAL_Status: The status of driver.
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*/
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HAL_Status HAL_PWM_OutputPluse(PWM_CH_ID ch_id);
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/**
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* @brief Enable the complementary.
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* @param group_id: The pwm group id.
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* @param en: set 1 enable , 0 disable.
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* @retval HAL_Status: The status of driver.
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*/
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HAL_Status HAL_PWM_EnableComplementary(PWM_GROUP_ID group_id, uint8_t en);
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/**
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* @brief Enable the pwm channel's interrupt.
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* @param ch_id: The pwm channel id.
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* @param param:
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* @arg param->event:The interrupt event.
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* @arg param->callback:The interrupt callback.
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* @arg param->arg: The param for callback.
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* @retval HAL_Status: The status of driver.
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*/
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HAL_Status HAL_PWM_EnableIRQ(PWM_CH_ID ch_id, const PWM_IrqParam *param);
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/**
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* @brief Disable the pwm channel's interrupt.
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* @param ch_id: The pwm channel id.
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* @retval HAL_Status: The status of driver.
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*/
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void HAL_PWM_DisableIRQ(PWM_CH_ID ch_id);
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/**
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* @brief Set channel's duty ratio.
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* @param ch_id: The pwm channel id.
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* @param value: The duty ratio value.
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* @retval HAL_Status: The status of driver.
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*/
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HAL_Status HAL_PWM_ChSetDutyRatio(PWM_CH_ID ch_id, uint16_t value);
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/**
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* @brief Set Complementary duty ratio.
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* @param group_id: The pwm group id.
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* @param value: The duty ratio value.
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* @retval HAL_Status: The status of driver.
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*/
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HAL_Status HAL_PWM_ComplementarySetDutyRatio(PWM_GROUP_ID group_id, uint16_t value);
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/**
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* @brief Set dead zone for complementary mode.
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* @param group_id: The pwm group id.
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* @param value: The dead zone value.
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* @retval HAL_Status: The status of driver.
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*/
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HAL_Status HAL_PWM_SetDeadZoneTime(PWM_GROUP_ID group_id, uint8_t dead_zone_value);
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/**
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* @brief Enable the dead zone.
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* @param group_id: The pwm group id.
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* @param en: set 1 enable, 0 disable.
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* @retval HAL_Status: The status of driver.
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*/
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HAL_Status HAL_PWM_EnableDeadZone(PWM_GROUP_ID group_id, uint8_t en);
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/**
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* @brief The pwm channel capture result.
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* @param mode:
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* @arg PWM_CAP_PLUSE: used for capture pluse. Run in the mode,
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* only the highLevlTime is valid.
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* @arg PWM_CAP_CYCLE: used for cycle signal. capture the signal's period,
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* high level time and low level time.
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* @param ch_id: The pwm channel id.
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* @retval PWM_CapResult: The result of capture.
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*/
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PWM_CapResult HAL_PWM_CaptureResult(PWM_CaptureMode mode, PWM_CH_ID ch_id);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _DRIVER_CHIP_HAL_PWM_H_ */
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