342 lines
12 KiB
C
Executable File
342 lines
12 KiB
C
Executable File
/**
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* @file hal_scr.h
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* @author XRADIO IOT WLAN Team
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*/
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/*
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* Copyright (C) 2019 XRADIO TECHNOLOGY CO., LTD. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DRIVER_CHIP_HAL_SCR_H_
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#define _DRIVER_CHIP_HAL_SCR_H_
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#include "driver/chip/hal_def.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define SCR_MDelay(ms) HAL_MSleep(ms)
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#define SCR_UDelay(us) HAL_UDelay(us)
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#define SCR_ATR_RESP_INVALID 0
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#define SCR_ATR_RESP_FAIL 1
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#define SCR_ATR_RESP_OK 2
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#define SCR_BUFFER_SIZE_MASK 0x3f /* 64 */
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/**
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* @brief SmartCard-Reader register block structure
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*/
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typedef struct {
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__IO uint32_t SCR_CSR; /* offset: 0x00, SmartCard-Reader control and status register */
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__IO uint32_t SCR_INT_EN; /* offset: 0x04, SmartCard-Reader interrupt enable register */
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__IO uint32_t SCR_INT_ST; /* offset: 0x08, SmartCard-Reader interrupt status register */
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__IO uint32_t SCR_FIFO_CSR; /* offset: 0x0C, SmartCard-Reader FIFO control and status register */
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__IO uint32_t SCR_FIFO_CNT; /* offset: 0x10, SmartCard-Reader FIFO counter register */
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__IO uint32_t SCR_FIFO_REPEAT; /* offset: 0x14, SmartCard-Reader repeat control register */
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__IO uint32_t SCR_CLKDIV; /* offset: 0x18, SmartCard-Reader clock divisor register */
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__IO uint32_t SCR_LTIM; /* offset: 0x1C, SmartCard-Reader line time register */
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__IO uint32_t SCR_CTIM; /* offset: 0x20, SmartCard-Reader character register */
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uint32_t RESERVED1[3];
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__IO uint32_t SCR_PAD; /* offset: 0x30, SmartCard-Reader line control register */
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uint32_t RESERVED2[2];
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__I uint32_t SCR_FSM; /* offset: 0x3C, SmartCard-Reader FSM register */
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__IO uint32_t SCR_DT; /* offset: 0x40, SmartCard-Reader debounce time register */
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uint32_t RESERVED3[47];
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__IO uint32_t SCR_FIFO_DATA; /* offset: 0x100, SmartCard-Reader FIFO data register */
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} SCREADER_T;
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#define SCREDAER ((SCREADER_T *)ISO7816_CTRL_BASE)
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#define SCR_FIFO_DEPTH 16
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/* SCREDAER->SCR_CSR */
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#define SCR_DETECT_BIT HAL_BIT(31)
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#define SCR_DETECT_POL_HIGH HAL_BIT(24)
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#define SCR_PROTOCOL_SELECT_SHIFT 22
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#define SCR_PROTOCOL_SELECT_MASK (0x3UL << SCR_PROTOCOL_SELECT_SHIFT)
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typedef enum {
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SCR_PROTOCOL_T0 = 0UL,
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SCR_PROTOCOL_T1,
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} SCR_PROTOL_SEL;
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#define SCR_ATR_ST_FLUSH_FIFO_BIT HAL_BIT(21)
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#define SCR_TS_RX_EN HAL_BIT(20)
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#define SCR_CLK_STOP_PROTOL_BIT HAL_BIT(19)
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#define SCR_PARITY_ERR_RX_EN HAL_BIT(18)
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#define SCR_MSB_FIRST_EN HAL_BIT(17)
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#define SCR_DATA_POL_BIT HAL_BIT(16)
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#define SCR_DEACT_BIT HAL_BIT(11)
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#define SCR_ACT_BIT HAL_BIT(10)
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#define SCR_WARM_RESET_BIT HAL_BIT(9)
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#define SCR_CLK_STOP_BIT HAL_BIT(8)
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#define SCR_GINT_EN HAL_BIT(2)
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#define SCR_RX_EN HAL_BIT(1)
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#define SCR_TX_EN HAL_BIT(0)
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/* SCREDAER->SCR_INT_EN & SCREDAER->SCR_INT_ST */
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#define SCR_INT_ALL_MASK 0xFF1E1FUL
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#define SCR_INT_DEACT HAL_BIT(23)
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#define SCR_INT_ACT HAL_BIT(22)
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#define SCR_INT_INSERT HAL_BIT(21)
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#define SCR_INT_REMOVE HAL_BIT(20)
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#define SCR_INT_ATR_DONE HAL_BIT(19)
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#define SCR_INT_ATR_FAIL HAL_BIT(18)
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#define SCR_INT_C2CFULL HAL_BIT(17) /* Character Timout */
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#define SCR_INT_CLOCK_STOPRUN HAL_BIT(16)
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#define SCR_INT_RXPARITY_ERR HAL_BIT(12)
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#define SCR_INT_RX_DONE HAL_BIT(11)
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#define SCR_INT_RXFIFO_THR HAL_BIT(10)
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#define SCR_INT_RXFIFO_FULL HAL_BIT(9)
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#define SCR_INT_TXPARITY_ERR HAL_BIT(4)
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#define SCR_INT_TX_DONE HAL_BIT(3)
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#define SCR_INT_TXFIFO_THR HAL_BIT(2)
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#define SCR_INT_TXFIFO_EMPTY HAL_BIT(1)
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#define SCR_INT_TXFIFO_DONE HAL_BIT(0)
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/* SCREDAER->SCR_FIFO_CSR */
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#define SCR_FLUSH_RXFIFO HAL_BIT(10)
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#define SCR_RXFIFO_FULL HAL_BIT(9)
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#define SCR_RXFIFO_EMPTY HAL_BIT(8)
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#define SCR_FLUSH_TXFIFO HAL_BIT(2)
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#define SCR_TXFIFO_FULL HAL_BIT(1)
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#define SCR_TXFIFO_EMPTY HAL_BIT(0)
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/* SCREDAER->SCR_FIFO_CNT */
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#define SCR_FIFO_CNT_MASK 0xFFUL
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#define SCR_RXFIFO_THR_SHIFT 24
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#define SCR_TXFIFO_THR_SHIFT 16
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#define SCR_RXFIFO_CNT_SHIFT 8
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#define SCR_TXFIFO_CNT_SHIFT 0
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/* SCREDAER->SCR_FIFO_REPEAT */
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#define SCR_REPEAT_MASK 0xFUL
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#define SCR_RX_REPEAT_NUM_SHIFT 4
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#define SCR_TX_REPEAT_NUM_SHIFT 0
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/* SCREDAER->SCR_CLKDIV */
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#define SCR_CLKDIV_MASK 0xFFFFUL
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#define SCR_BAUD_DIV_SHIFT 16
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#define SCR_MCLK_DIV_SHIFT 0
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/* SCREDAER->SCR_LTIM */
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#define SCR_LTIM_8BTI_MASK 0xFFUL
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#define SCR_LTIM_ATR_SHIFT 16
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#define SCR_LTIM_RST_SHIFT 8
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#define SCR_LTIM_ACT_SHIFT 0
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/* SCREDAER->SCR_CTIM */
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#define SCR_CTIM_CHARLIMT_MASK 0xFFFFUL
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#define SCR_CTIM_CHARLIMT_SHIFT 16
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#define SCR_CTIM_GUARDTIME_MASK 0xFFUL
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#define SCR_CTIM_GUARDTIME_SHIFT 0
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/* SCREDAER->SCR_PAD */
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#define SCR_PAD_DSCVPP_PP HAL_BIT(7)
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#define SCR_PAD_DSCVPP_EN HAL_BIT(6)
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#define SCR_PAD_AUTO_ACT_VPP HAL_BIT(5)
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#define SCR_PAD_DSC_VCC HAL_BIT(4)
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#define SCR_PAD_DSC_RST HAL_BIT(3)
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#define SCR_PAD_DSC_CLK HAL_BIT(2)
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#define SCR_PAD_DSC_IO HAL_BIT(1)
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#define SCR_PAD_DIR_AC_PADS HAL_BIT(0)
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/* SCREDAER->SCR_FSM */
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#define SCR_RSM_8BIT_MASK 0xFFUL
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#define SCR_FSM_ATR_STRUCT (SCR_RSM_8BIT_MASK << 24)
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#define SCR_FSM_ATR (SCR_RSM_8BIT_MASK << 16)
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#define SCR_FSM_ACT (SCR_RSM_8BIT_MASK << 8)
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#define SCR_FSM_SCR (SCR_RSM_8BIT_MASK << 0)
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/* SCREDAER->SCR_FIFO_DATA */
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#define SCR_FIFO_DATA_MASK 0xFFUL
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/* SCR Card State FSM */
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#define SCR_CARD_IDLE 0x0
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#define SCR_CARD_ACT 0x1
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#define SCR_CARD_ATR 0x2
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#define SCR_CARD_DATA 0x3
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#define SCR_CARD_DEACT 0x4
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/* SCR Active/Deactive State FSM */
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#define SCR_ACT_INACTIVE 0x0
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#define SCR_ACT_A1 0x1 /* Vcc shall be powered */
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#define SCR_ACT_A2 0x2 /* I/O shall be put in reception mode */
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#define SCR_ACT_A3 0x3 /* Vpp shall be raised to idle state (if AutoVPP) */
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#define SCR_ACT_ACTIVE 0x4 /* CLK shall be provided with a suitable and stable clock */
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#define SCR_ACT_D1 0x5 /* State L on RST */
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#define SCR_ACT_D2 0x6 /* State L on CLK */
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#define SCR_ACT_D3 0x7 /* Vpp inactive (if AutoVPP) */
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#define SCR_ACT_D4 0x8 /* State A on I/O */
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#define SCR_ACT_D5 0x9 /* Vcc inactive */
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/* SCR ATR State FSM */
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#define SCR_ATR_IDLE 0x0
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#define SCR_ATR_RST 0x1
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#define SCR_ATR_WAIT 0x2
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#define SCR_ATR_START 0x3
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#define SCR_ATR_DONEx 0x4
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#define SCR_ATR_FAILx 0x5
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/* SCR ATR Structure State FSM */
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#define SCR_STR_IDLE 0x0
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#define SCR_STR_TS 0x1
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#define SCR_STR_T0 0x2
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#define SCR_STR_TX 0x3
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#define SCR_STR_TK 0x4
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#define SCR_STR_TCK 0x5
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#define SCR_STR_DONE 0x6
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#define SCR_STR_FAIL 0x7
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#define SCR_FSM_MAX_RECORD 1024
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typedef struct {
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uint32_t count;
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uint32_t old;
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uint32_t record[SCR_FSM_MAX_RECORD];
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} scr_fsm_record, *pscr_fsm_record;
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typedef struct {
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uint8_t TS;
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uint8_t TK[15];
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uint8_t TK_NUM;
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uint32_t T; /*Protocol */
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uint32_t FMAX; /*in MHz */
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uint32_t F;
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uint32_t D;
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uint32_t I; /* Max Cunrrent for Program, in mA */
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uint32_t P; /* Program Voltage */
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uint32_t N; /* Extra Guard Time, in ETUs */
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} scatr_struct, *pscatr_struct;
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typedef struct {
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uint8_t ppss;
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uint8_t pps0;
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uint8_t pps1;
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uint8_t pps2;
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uint8_t pps3;
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uint8_t pck;
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} upps_struct, *ppps_struct;
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typedef enum {
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STS_WAIT_CONNECT = 0,
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STS_WAIT_ACT,
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STS_WAIT_ATR,
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STS_WARM_RESET,
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STS_WAIT_ATR_AGAIN,
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STS_START_PPS,
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STS_WAIT_PPS_RESP,
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STS_SEND_CMD,
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STS_START_DEACT,
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STS_WAIT_DEACT,
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STS_WAIT_DISCONNECT,
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STS_IDLE,
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STS_RW_TEST,
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} SCR_TEST_STAGE;
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/** @brief Type define of QDEC interrupt callback function */
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typedef void (*SCR_IRQCallback)(void *arg);
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/**
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* @brief SCR initialization parameters
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*/
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typedef struct {
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uint32_t mclk; /* smart card clock frequency */
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uint8_t fifo_thr; /* tx & rx fifo threshold */
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uint8_t repeat_num; /* the re-transmission time when wrong parity */
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uint8_t act_time; /* activation/deactivation time */
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uint8_t rst_time; /* reset duration */
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uint8_t atr_time; /* atr start limit */
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uint8_t guard_time; /* character guard time */
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uint32_t char_limit; /* character limit */
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SCR_IRQCallback IRQCallback;
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void *arg;
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} SCR_InitParam;
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/* write cmd and read data immediately */
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typedef struct {
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uint8_t *cmd_buf;
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uint32_t cmd_len;
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uint8_t *rtn_data;
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uint32_t rtn_len;
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uint8_t psw1;
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uint8_t psw2;
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} SCR_WRData;
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/**
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* @brief Initialize the SCR
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* @retval HAL_Status, HAL_OK on success
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*/
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HAL_Status HAL_SCR_Init(SCR_InitParam *initParam);
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/**
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* @brief DeInitialize the SCR
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* @retval HAL_Status, HAL_OK on success
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*/
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HAL_Status HAL_SCR_DeInit(void);
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SCR_TEST_STAGE HAL_SCR_Process(SCR_InitParam *initParam);
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/**
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* @brief SCR write the assigned length data, send in polling mode
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* @retval Number of bytes transmitted, -1 on error
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*/
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int32_t HAL_SCR_SendByPoll(uint8_t *buf, int32_t size);
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/**
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* @brief SCR write the assigned length data, suspend current thread until send finish
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* @retval Number of bytes transmitted, -1 on error
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*/
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int32_t HAL_SCR_SendByIT(uint8_t *buf, int32_t size);
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/**
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* @brief SCR read the assigned length data, suspend current thread until received finish
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* @retval Number of bytes received, -1 on error
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*/
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int32_t HAL_SCR_ReceiveByIT(uint8_t *buf, int32_t size);
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/**
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* @brief Send APDU command to card, and receive data from card
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* @param[in] apdu_t load apdu command parameters
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* @return 0 on success, -1 on error
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* @note APDU, smart card cammand format:
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* send format:
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* type1: CLS + INS + P1 + P2 + le -> only read, le=read size
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* type2: CLS + INS + P1 + P2 + lc + data only lc, write data, lc=data size
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* type3: CLS + INS + P1 + P2 + lc + data +le -> le + lc
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* respond format:
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* type1: INS(apdu_t->cmd_buf[1]) + valid_data(apdu_t->cmd_buf[4]) + SW1 + SW2
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* type2: INS + SW1 + SW2
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* type3: INS + valid_data + SW1 + SW2
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*/
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HAL_Status HAL_SCR_APDUCmd(SCR_WRData *apdu_t);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _DRIVER_CHIP_HAL_SCR_H_ */
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