173 lines
7.4 KiB
C
Executable File
173 lines
7.4 KiB
C
Executable File
/**
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* @file hal_wdg.h
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* @author XRADIO IOT WLAN Team
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*/
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/*
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* Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DRIVER_CHIP_HAL_SYSCTL_H_
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#define _DRIVER_CHIP_HAL_SYSCTL_H_
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#include "driver/chip/hal_def.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief SYSCTL register block structure
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*/
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typedef struct {
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uint32_t RESERVED0[17]; /* offset: 0x00 */
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__IO uint32_t SIP_TEST_MAP; /* offset: 0x44 */
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__IO uint32_t SRAM_SHARE; /* offset: 0x48 */
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uint32_t RESERVED1; /* offset: 0x4C */
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__IO uint32_t PS_CTL_REG; /* offset: 0x50 */
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__IO uint32_t PS_CNT_REG; /* offset: 0x54 */
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#if (CONFIG_CHIP_ARCH_VER == 2)
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uint32_t RESERVED2[22]; /* offset: 0x58 */
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#elif (CONFIG_CHIP_ARCH_VER == 3)
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uint32_t RESERVED58[2]; /* offset: 0x58 */
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__IO uint32_t FLASH_PSRAM_PIN_MAP_REG; /* offset: 0x60 */
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uint32_t RESERVED64[19]; /* offset: 0x64 */
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#endif
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__IO uint32_t GENRAL_DBG_REG[2]; /* offset: 0xB0 */
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} SYSCTL_T;
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#define SYSCTL ((SYSCTL_T *)SYSCTL_BASE) /* address: 0x4000A000 */
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/* SYSCTL->SRAM_SHARE 0x48 */
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#define SYSCTL_PIN_MCU_MODE_SHIFT (16)
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#define SYSCTL_PIN_MCU_MODE_EN (0x1 << SYSCTL_PIN_MCU_MODE_SHIFT)
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#if (CONFIG_CHIP_ARCH_VER == 2)
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#define SYSCTL_CSI_JPEG_SHARE_SRAM_SHIFT (8)
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#define SYSCTL_CSI_JPEG_SHARE_SRAM_MASK (0x3 << SYSCTL_CSI_JPEG_SHARE_SRAM_SHIFT)
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typedef enum {
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SYSCTL_CSI_JPEG_SHARE_NONE = (0 << SYSCTL_CSI_JPEG_SHARE_SRAM_SHIFT),
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SYSCTL_CSI_JPEG_SHARE_32K = (1 << SYSCTL_CSI_JPEG_SHARE_SRAM_SHIFT),
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SYSCTL_CSI_JPEG_SHARE_64K = (2 << SYSCTL_CSI_JPEG_SHARE_SRAM_SHIFT),
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} SYSCTL_CSI_JPEG_ShareSramType;
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#define SYSCTL_WLAN_SHARE_SRAM_SHIFT (0)
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#define SYSCTL_WLAN_SHARE_SRAM_MASK (0x7 << SYSCTL_WLAN_SHARE_SRAM_SHIFT)
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typedef enum {
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SYSCTL_WLAN_SHARE_NONE = (0 << SYSCTL_WLAN_SHARE_SRAM_SHIFT),
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SYSCTL_WLAN_SHARE_32K = (1 << SYSCTL_WLAN_SHARE_SRAM_SHIFT),
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SYSCTL_WLAN_SHARE_64K = (2 << SYSCTL_WLAN_SHARE_SRAM_SHIFT),
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SYSCTL_WLAN_SHARE_96K = (3 << SYSCTL_WLAN_SHARE_SRAM_SHIFT),
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SYSCTL_WLAN_SHARE_128K = (4 << SYSCTL_WLAN_SHARE_SRAM_SHIFT),
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} SYSCTL_WLAN_ShareSramType;
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#endif
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/* SYSCTL->PS_CTL_REG 0x50 */
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#define SYSCTL_CLK250M_CNT_RDY_SHIFT (16)
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#define SYSCTL_CLK250M_CNT_RDY_MASK (0x1 << SYSCTL_CLK250M_CNT_RDY_SHIFT)
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#define SYSCTL_DEVICE_SEL_SHIFT (8)
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#define SYSCTL_DEVICE_SEL_MASK (0x7 << SYSCTL_DEVICE_SEL_SHIFT)
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typedef enum {
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SYSCTL_PSENSOR_0 = (0U << SYSCTL_DEVICE_SEL_SHIFT),
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SYSCTL_PSENSOR_1 = (1U << SYSCTL_DEVICE_SEL_SHIFT),
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} SYSCTL_PsensorId;
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#define SYSCTL_PS_EN_SEL_SHIFT (4)
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#define SYSCTL_PS_EN_SEL_MASK (0x3 << SYSCTL_PS_EN_SEL_SHIFT)
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typedef enum {
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SYSCTL_OSC_DISABLE = (0U << SYSCTL_PS_EN_SEL_SHIFT),
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SYSCTL_OSC_RVT_CASECODE = (1U << SYSCTL_PS_EN_SEL_SHIFT),
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SYSCTL_OSC_LVT_CASECODE = (2U << SYSCTL_PS_EN_SEL_SHIFT),
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SYSCTL_OSC_RVT_NORMAL = (3U << SYSCTL_PS_EN_SEL_SHIFT),
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} SYSCTL_OSCSelect;
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#define SYSCTL_PS_N_PRD_SHIFT (1)
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#define SYSCTL_PS_N_PRD_MASK (0x7 << SYSCTL_PS_N_PRD_SHIFT)
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#define SYSCTL_PS_N_PRD_VAL(v) ((v & 0x7) << SYSCTL_PS_N_PRD_SHIFT)
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#define SYSCTL_PS_EN_SHIFT (0)
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#define SYSCTL_PS_EN_MASK (0x1 << SYSCTL_PS_EN_SHIFT)
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#if (CONFIG_CHIP_ARCH_VER == 3)
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/* SYSCTL->FLASH_PSRAM_PIN_MAP_REG 0x60 */
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/* GPIOB08 ~ GPIOB11 */
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#define SYSCTL_FLASH_PSRAM_PIN_MAP1_SHIFT (16)
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#define SYSCTL_FLASH_PSRAM_PIN_MAP1_MASK (0x3 << SYSCTL_FLASH_PSRAM_PIN_MAP1_SHIFT)
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typedef enum {
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SYSCTL_FLASH_PSRAM_PIN_MAP1_RESERVED = (0U << SYSCTL_FLASH_PSRAM_PIN_MAP1_SHIFT),
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SYSCTL_FLASH_PSRAM_PIN_MAP1_ONLY_CS0 = (1U << SYSCTL_FLASH_PSRAM_PIN_MAP1_SHIFT),
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SYSCTL_FLASH_PSRAM_PIN_MAP1_ONLY_CS1 = (2U << SYSCTL_FLASH_PSRAM_PIN_MAP1_SHIFT),
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SYSCTL_FLASH_PSRAM_PIN_MAP1_BOTH_CS0_1 = (2U << SYSCTL_FLASH_PSRAM_PIN_MAP1_SHIFT),
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} SYSCTL_FlashPsramPinMap1;
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/* GPIOB02 ~ GPIOB05 */
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#define SYSCTL_FLASH_PSRAM_PIN_MAP0_SHIFT (0)
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#define SYSCTL_FLASH_PSRAM_PIN_MAP0_MASK (0x3 << SYSCTL_FLASH_PSRAM_PIN_MAP0_SHIFT)
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typedef enum {
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SYSCTL_FLASH_PSRAM_PIN_MAP0_RESERVED = (0U << SYSCTL_FLASH_PSRAM_PIN_MAP0_SHIFT),
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SYSCTL_FLASH_PSRAM_PIN_MAP0_ONLY_CS0 = (1U << SYSCTL_FLASH_PSRAM_PIN_MAP0_SHIFT),
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SYSCTL_FLASH_PSRAM_PIN_MAP0_ONLY_CS1 = (2U << SYSCTL_FLASH_PSRAM_PIN_MAP0_SHIFT),
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SYSCTL_FLASH_PSRAM_PIN_MAP0_BOTH_CS0_1 = (2U << SYSCTL_FLASH_PSRAM_PIN_MAP0_SHIFT),
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} SYSCTL_FlashPsramPinMap0;
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#endif
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/* SYSCTL->SIP_TEST_MAP 0x44 */
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#define SYSCTL_SIP_TEST_MAP_WRITE_SHIFT (16)
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#define SYSCTL_SIP_TEST_MAP_WRITE_EN (0x429D << SYSCTL_SIP_TEST_MAP_WRITE_SHIFT)
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#define SYSCTL_SIP_FLASH_TEST_MAP_SHIFT (0)
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#define SYSCTL_SIP_FLASH_TEST_MAP_EN (0x1 << SYSCTL_SIP_FLASH_TEST_MAP_SHIFT)
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#define SYSCTL_SIP_PSRAM_TEST_MAP_SHIFT (1)
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#define SYSCTL_SIP_PSRAM_TEST_MAP_EN (0x1 << SYSCTL_SIP_PSRAM_TEST_MAP_SHIFT)
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void HAL_SYSCTL_SetMcuMode(uint32_t en);
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#if (CONFIG_CHIP_ARCH_VER == 2)
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void HAL_SYSCTL_SetWlanSramShare(SYSCTL_WLAN_ShareSramType type);
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void HAL_SYSCTL_SetCSIJPEGSramShare(SYSCTL_CSI_JPEG_ShareSramType mode);
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#endif
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void HAL_SYSCTL_SetPsensorControl(SYSCTL_PsensorId id, SYSCTL_OSCSelect osc_sel,
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uint32_t ps_n, uint32_t en);
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void HAL_SYSCTL_WaitPsensorRdyAndClean(void);
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uint32_t HAL_SYSCTL_GetPsensorCnt(void);
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#if (CONFIG_CHIP_ARCH_VER == 3)
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void HAL_SYSCTL_SelectFlashPsramPinMap(SYSCTL_FlashPsramPinMap0 cs0, SYSCTL_FlashPsramPinMap1 cs1);
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#endif
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void HAL_SYSCTL_SetDbgData(uint32_t id, uint32_t data);
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uint32_t HAL_SYSCTL_GetDegData(uint32_t id);
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uint32_t HAL_SYSCTL_GetPsensor(uint32_t id);
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void HAL_SYSCTL_SetSipFlashTestMapMode(void);
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void HAL_SYSCTL_SetSipPsramTestMapMode(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _DRIVER_CHIP_HAL_SYSCTL_H_ */
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