223 lines
7.4 KiB
C
Executable File
223 lines
7.4 KiB
C
Executable File
/**
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* @file hal_wdg.h
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* @author XRADIO IOT WLAN Team
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*/
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/*
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* Copyright (C) 2017 XRADIO TECHNOLOGY CO., LTD. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name of XRADIO TECHNOLOGY CO., LTD. nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DRIVER_CHIP_HAL_WDG_H_
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#define _DRIVER_CHIP_HAL_WDG_H_
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#include "driver/chip/hal_def.h"
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#if (CONFIG_CHIP_ARCH_VER > 1)
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#include "driver/chip/hal_prcm.h"
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#include "driver/chip/hal_ccm.h"
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Options of supporting watchdog interrupt mode */
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#if (CONFIG_CHIP_ARCH_VER > 1)
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#define HAL_WDG_INTERRUPT_SUPPORT 1
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#else
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#define HAL_WDG_INTERRUPT_SUPPORT 0
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#endif
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/**
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* @brief Watchdog register block structure
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*/
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typedef struct {
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__IO uint32_t IRQ_EN; /* offset: 0xA0, Watchdog IRQ Enable Register */
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__IO uint32_t IRQ_STATUS; /* offset: 0xA4, Watchdog IRQ Status Register */
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uint32_t RESERVED0[2];
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__IO uint32_t CTRL; /* offset: 0xB0, Watchdog Control Register */
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__IO uint32_t CFG; /* offset: 0xB4, Watchdog Configuration Register */
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__IO uint32_t MODE; /* offset: 0xB8, Watchdog Mode Register */
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__IO uint32_t RESET_CTRL; /* offset: 0xBC, Watchdog Output Control Register */
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} WDG_T;
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#define WDG ((WDG_T *)(TIMER_BASE + 0xA0)) /* address: 0x400408A0 */
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/* WDG->IRQ_EN */
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#define WDG_IRQ_EN_BIT HAL_BIT(0)
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/* WDG->IRQ_STATUS */
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#define WDG_IRQ_PENDING_BIT HAL_BIT(0)
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/* WDG->CFG */
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#if (CONFIG_CHIP_ARCH_VER > 1)
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#define WDG_RESET_CPU_MODE_SHIFT 2
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#define WDG_RESET_CPU_MODE_MASK (0x3U << WDG_RESET_CPU_MODE_SHIFT)
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typedef enum {
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WDG_RESET_CPU_PORESET = (0U << WDG_RESET_CPU_MODE_SHIFT), /* reset the cpu PORESETn */
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WDG_RESET_CPU_SYSRESET = (1U << WDG_RESET_CPU_MODE_SHIFT), /* reset the cpu SYSRESETn */
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WDG_RESET_CPU_CORE = (2U << WDG_RESET_CPU_MODE_SHIFT), /* reset the cpu core, PORESETn & SYSRESETn */
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} WDG_ResetCpuMode;
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#endif
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#define WDG_EVT_TYPE_SHIFT 0
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#define WDG_EVT_TYPE_MASK (0x3U << WDG_EVT_TYPE_SHIFT)
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typedef enum {
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#if (CONFIG_CHIP_ARCH_VER > 1)
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WDG_EVT_RESET_CPU = (0U << WDG_EVT_TYPE_SHIFT), /* reset cpu */
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#endif
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WDG_EVT_RESET = (1U << WDG_EVT_TYPE_SHIFT), /* reset system */
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WDG_EVT_INTERRUPT = (2U << WDG_EVT_TYPE_SHIFT) /* trigger interrupt */
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} WDG_EventType;
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/* WDG->MODE */
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#define WDG_TIMEOUT_SHIFT 4
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#define WDG_TIMEOUT_MASK (0xF << WDG_TIMEOUT_SHIFT)
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typedef enum {
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WDG_TIMEOUT_500MS = (0U << WDG_TIMEOUT_SHIFT),
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WDG_TIMEOUT_1SEC = (1U << WDG_TIMEOUT_SHIFT),
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WDG_TIMEOUT_2SEC = (2U << WDG_TIMEOUT_SHIFT),
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WDG_TIMEOUT_3SEC = (3U << WDG_TIMEOUT_SHIFT),
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WDG_TIMEOUT_4SEC = (4U << WDG_TIMEOUT_SHIFT),
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WDG_TIMEOUT_5SEC = (5U << WDG_TIMEOUT_SHIFT),
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WDG_TIMEOUT_6SEC = (6U << WDG_TIMEOUT_SHIFT),
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WDG_TIMEOUT_8SEC = (7U << WDG_TIMEOUT_SHIFT),
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WDG_TIMEOUT_10SEC = (8U << WDG_TIMEOUT_SHIFT),
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WDG_TIMEOUT_12SEC = (9U << WDG_TIMEOUT_SHIFT),
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WDG_TIMEOUT_14SEC = (10U << WDG_TIMEOUT_SHIFT),
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WDG_TIMEOUT_16SEC = (11U << WDG_TIMEOUT_SHIFT)
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} WDG_Timeout;
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#define WDG_MIN_TIMEOUT_US 500000
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#if (CONFIG_CHIP_ARCH_VER > 1)
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#define WDG_RESET_IMMED_SHIFT 1
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#define WDG_RESET_IMMED_MASK (0x7 << WDG_RESET_IMMED_SHIFT)
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#define WDG_RESET_IMMED_VAL (0x6 << WDG_RESET_IMMED_SHIFT)
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#endif
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#define WDG_EN_BIT HAL_BIT(0)
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/* WDG->RESET_CTRL */
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#define WDG_RESET_CYCLE_SHIFT 0
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#define WDG_RESET_CYCLE_MASK (0x1F << WDG_RESET_CYCLE_SHIFT)
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#define WDG_DEFAULT_RESET_CYCLE 0xA
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/******************************************************************************/
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#if HAL_WDG_INTERRUPT_SUPPORT
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/** @brief Type define of watchdog IRQ callback function */
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typedef void (*WDG_IRQCallback) (void *arg);
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#endif
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/**
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* @brief Watchdog h/w initialization parameters
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*/
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typedef struct {
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WDG_EventType event; /* Watchdog trigger event type */
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#if (CONFIG_CHIP_ARCH_VER > 1)
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WDG_ResetCpuMode resetCpuMode; /* reset cpu mode, for WDG_EVT_RESET_CPU only */
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#endif
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WDG_Timeout timeout; /* Interval to trigger event after last feed */
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uint8_t resetCycle; /* Reset signal cycles, for WDG_EVT_RESET and WDG_EVT_RESET_CPU.
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Set to WDG_DEFAULT_RESET_CYCLE generally, its range is [0, 31] */
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} WDG_HwInitParam;
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/**
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* @brief Watchdog initialization parameters
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*/
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typedef struct {
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WDG_HwInitParam hw;
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#if HAL_WDG_INTERRUPT_SUPPORT
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WDG_IRQCallback callback; /* Watchdog IRQ callback fucntion, for WDG_EVT_INTERRUPT only */
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void *arg; /* Argument of Watchdog IRQ callback fucntion, for WDG_EVT_INTERRUPT only */
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#endif
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} WDG_InitParam;
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/**
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* @brief Initialize the watchdog according to the specified parameters
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* @param[in] param Pointer to WDG_InitParam structure
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* @retval HAL_Status, HAL_OK on success
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*/
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HAL_Status HAL_WDG_Init(const WDG_InitParam *param);
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/**
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* @brief DeInitialize the watchdog
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* @retval HAL_Status, HAL_OK on success
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*/
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HAL_Status HAL_WDG_DeInit(void);
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/**
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* @brief Feed the watchdog
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* @note When watchdog running, reset system or IRQ event will be triggered if
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* no feeding executed in the interval configured by HAL_WDG_Init().
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* @return None
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*/
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void HAL_WDG_Feed(void);
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/**
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* @brief Start the watchdog
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* @return None
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*/
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void HAL_WDG_Start(void);
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/**
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* @brief Stop the watchdog
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* @return None
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*/
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void HAL_WDG_Stop(void);
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/**
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* @brief Reboot system using the watchdog
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* @return None
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*/
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void HAL_WDG_Reboot(void);
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/**
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* @brief Reset cpu using the watchdog
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* @return None
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*/
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void HAL_WDG_ResetCpu(WDG_ResetCpuMode mode);
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/**
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* @brief Set peripherals which will not be reset when watchdog reset cpu
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* @param[in] periphMask Bitmask of peripherals, refer to CCM_BusPeriphBit
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* @param[in] enable
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* @arg !0 Enable peripherals which will not be reset
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* @arg 0 Disable peripherals which will not be reset
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* @return None
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*/
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static __always_inline void HAL_WDG_SetNoResetPeriph(uint32_t periphMask, int8_t enable)
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{
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HAL_PRCM_SetWdgNoResetPeriph(periphMask, enable);
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* _DRIVER_CHIP_HAL_WDG_H_ */
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