159 lines
4.2 KiB
C
Executable File
159 lines
4.2 KiB
C
Executable File
#ifndef _ROM_RAM_TABLE_H_
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#define _ROM_RAM_TABLE_H_
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#ifdef CONFIG_ROM
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#define RAM_TBL_IDX(name) RAM_TBL_IDX_##name
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#define RAM_TBL_FUN(prototype, name) \
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((prototype)(ram_table[RAM_TBL_IDX(name)]))
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#define RAM_TBL_DATA(type, name) \
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((type)(ram_table[RAM_TBL_IDX(name)]))
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extern unsigned int ram_table[];
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enum {
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/* internal used by rom only */
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/* chip */
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RAM_TBL_IDX(SYS_PLL_CLOCK),
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RAM_TBL_IDX(SYS_LFCLOCK),
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RAM_TBL_IDX(HAL_PRCM_GetHFClock),
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RAM_TBL_IDX(HAL_PRCM_GetLFClock),
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RAM_TBL_IDX(HAL_PRCM_GetDevClock),
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RAM_TBL_IDX(HAL_CCM_BusGetAPBSClock),
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/* lib */
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RAM_TBL_IDX(__wrap__malloc_r),
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RAM_TBL_IDX(__wrap__realloc_r),
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RAM_TBL_IDX(__wrap__free_r),
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RAM_TBL_IDX(_sbrk),
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RAM_TBL_IDX(__wrap_vprintf),
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RAM_TBL_IDX(__wrap_puts),
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RAM_TBL_IDX(__wrap_vfprintf),
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RAM_TBL_IDX(__wrap_fputs),
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RAM_TBL_IDX(__wrap_putchar),
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RAM_TBL_IDX(__wrap_putc),
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RAM_TBL_IDX(__wrap_fputc),
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RAM_TBL_IDX(__wrap_fflush),
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/* FreeRTOS */
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RAM_TBL_IDX(configMINIMAL_STACK_SIZE),
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RAM_TBL_IDX(configTIMER_QUEUE_LENGTH),
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RAM_TBL_IDX(configTIMER_TASK_STACK_DEPTH),
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RAM_TBL_IDX(vApplicationStackOverflowHook),
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RAM_TBL_IDX(portALLOCATE_SECURE_CONTEXT),
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RAM_TBL_IDX(portCLEAN_UP_TCB),
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RAM_TBL_IDX(SecureContext_FreeContext),
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RAM_TBL_IDX(SecureContext_LoadContext),
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RAM_TBL_IDX(SecureContext_SaveContext),
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RAM_TBL_IDX(SecureContext_Init),
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RAM_TBL_IDX(vRestoreContextOfFirstTask),
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RAM_TBL_IDX(SecureInit_DePrioritizeNSExceptions),
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RAM_TBL_IDX(SecureContext_AllocateContext),
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RAM_TBL_IDX(pxPortInitialiseStack),
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RAM_TBL_IDX(SecureInit_EnableNSFPUAccess),
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/* OS */
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RAM_TBL_IDX(OS_SemaphoreCreate),
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RAM_TBL_IDX(OS_SemaphoreCreateBinary),
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RAM_TBL_IDX(OS_SemaphoreDelete),
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RAM_TBL_IDX(OS_SemaphoreWait),
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RAM_TBL_IDX(OS_SemaphoreRelease),
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RAM_TBL_IDX(OS_SemaphoreIsValid),
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RAM_TBL_IDX(OS_SemaphoreSetInvalid),
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RAM_TBL_IDX(OS_MutexCreate),
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RAM_TBL_IDX(OS_MutexDelete),
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RAM_TBL_IDX(OS_MutexLock),
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RAM_TBL_IDX(OS_MutexUnlock),
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RAM_TBL_IDX(OS_RecursiveMutexCreate),
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RAM_TBL_IDX(OS_RecursiveMutexDelete),
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RAM_TBL_IDX(OS_RecursiveMutexLock),
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RAM_TBL_IDX(OS_RecursiveMutexUnlock),
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RAM_TBL_IDX(OS_ThreadList),
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RAM_TBL_IDX(OS_ThreadSuspendScheduler),
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RAM_TBL_IDX(OS_ThreadResumeScheduler),
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RAM_TBL_IDX(OS_ThreadIsSchedulerRunning),
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RAM_TBL_IDX(OS_TimerCreate),
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RAM_TBL_IDX(OS_TimerDelete),
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RAM_TBL_IDX(OS_TimerStart),
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RAM_TBL_IDX(OS_TimerChangePeriod),
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RAM_TBL_IDX(OS_TimerStop),
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RAM_TBL_IDX(OS_TimerIsActive),
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RAM_TBL_IDX(OS_HZ),
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RAM_TBL_IDX(OS_GetTicks),
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RAM_TBL_IDX(OS_MSleep),
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RAM_TBL_IDX(HAL_UDelay),
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RAM_TBL_IDX(HAL_Alive),
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/* dma */
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RAM_TBL_IDX(HAL_DMA_Init),
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RAM_TBL_IDX(HAL_DMA_Start),
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RAM_TBL_IDX(HAL_DMA_Stop),
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RAM_TBL_IDX(HAL_DMA_FlashSbus_Iscoexist),
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RAM_TBL_IDX(dma_malloc),
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RAM_TBL_IDX(dma_free),
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RAM_TBL_IDX(dma_calloc),
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RAM_TBL_IDX(dma_realloc),
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/* image */
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RAM_TBL_IDX(flash_rw),
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RAM_TBL_IDX(flash_get_erase_block),
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RAM_TBL_IDX(flash_erase),
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RAM_TBL_IDX(fdcm_open),
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RAM_TBL_IDX(fdcm_read),
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RAM_TBL_IDX(fdcm_write),
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RAM_TBL_IDX(image_checksum16),
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RAM_TBL_IDX(image_get_addr),
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RAM_TBL_IDX(image_get_bl_size),
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/* nvic, check HAL_NVIC_SetIRQHandler is used in rom code! */
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RAM_TBL_IDX(HAL_NVIC_ConfigExtIRQ), /* for unify irq entry */
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/* flash */
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RAM_TBL_IDX(HAL_Flash_Open),
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RAM_TBL_IDX(HAL_Flash_Close),
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RAM_TBL_IDX(HAL_Flash_Write),
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RAM_TBL_IDX(HAL_Flash_Read),
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RAM_TBL_IDX(HAL_Flash_Erase),
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RAM_TBL_IDX(HAL_Flash_MemoryOf),
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RAM_TBL_IDX(flashcDriverCreate),
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RAM_TBL_IDX(spiDriverCreate),
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RAM_TBL_IDX(FlashChipGetCfgList),
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RAM_TBL_IDX(FlashChipGetChipList),
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RAM_TBL_IDX(defaultControl),
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RAM_TBL_IDX(HAL_Flashc_Delay),
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RAM_TBL_IDX(HAL_Flashc_Xip_Init),
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RAM_TBL_IDX(HAL_Flashc_Xip_Deinit),
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RAM_TBL_IDX(HAL_Flashc_Init),
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RAM_TBL_IDX(HAL_Flashc_Deinit),
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RAM_TBL_IDX(HAL_Flashc_Open),
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RAM_TBL_IDX(HAL_Flashc_Close),
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RAM_TBL_IDX(HAL_Flashc_Ioctl),
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RAM_TBL_IDX(HAL_Flashc_Transfer),
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RAM_TBL_IDX(FC_GetDelayCycle),
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RAM_TBL_IDX(FLASH_XIP_START_ADDR),
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RAM_TBL_IDX(FLASH_XIP_END_ADDR),
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RAM_TBL_IDX(FLASH_XIP_USER_START_ADDR),
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RAM_TBL_IDX(FLASH_XIP_USER_END_ADDR),
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RAM_TBL_IDX(PSRAM_START_ADDR),
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RAM_TBL_IDX(PSRAM_END_ADDR),
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RAM_TBL_IDX(FlashCBUS_AddrRequire),
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RAM_TBL_IDX(FlashCryptoRequest),
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/* pm */
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RAM_TBL_IDX(WakeIo_To_Gpio),
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RAM_TBL_IDX(pm_check_wakeup_irqs),
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RAM_TBL_IDX(cpu_suspend_cb),
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};
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#endif /* CONFIG_ROM */
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#endif /*_ROM_RAM_TABLE_H_*/
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