407 lines
8.9 KiB
C
407 lines
8.9 KiB
C
/*
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* (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
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*
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* (C) Copyright 2007-2011
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Tom Cubie <tangliang@allwinnertech.com>
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*
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* Some init for sunxi platform.
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*
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*/
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#include <common.h>
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#include <libfdt.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <linux/compiler.h>
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#include <linux/errno.h>
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#include <private_boot0.h>
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#include <arch/clock.h>
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#include <arch/uart.h>
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#include <arch/rtc.h>
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#include <arch/gpio.h>
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#ifdef CFG_BOOT0_LOAD_KERNEL
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void rtc_set_vccio_det_spare(void)
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{
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u32 val = 0;
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val = readl(SUNXI_RTC_BASE + 0x1f4);
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val &= ~(0xff << 4);
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val |= (VCCIO_THRESHOLD_VOLTAGE_2_9 | FORCE_DETECTER_OUTPUT);
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val &= ~VCCIO_DET_BYPASS_EN;
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writel(val, SUNXI_RTC_BASE + 0x1f4);
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}
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#endif
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#ifndef FPGA_PLATFORM
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int sunxi_board_init(void)
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{
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/*
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* When waking up, don't change the voltage, frequency,
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* cpu is easy to hang. We restore it in atf.
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*/
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/* set_pll_voltage(CONFIG_SUNXI_CORE_VOL); */
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#ifdef CFG_SUNXI_POWER
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if ((axp_init(0) >= 0) && (!super_standby_mode())) {
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int sys_vol = (get_power_mode() & 0x3f);
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int grain_size = get_power_mode() >> 6;
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if (sys_vol != 0) {
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switch (grain_size) {
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case 0:
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sys_vol = 500 + sys_vol * 10;
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break;
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case 1:
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sys_vol = 500 + sys_vol * 20;
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break;
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case 2:
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sys_vol = 500 + sys_vol * 50;
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break;
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case 3:
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sys_vol = 500 + sys_vol * 100;
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break;
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}
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if (sys_vol < 900)
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sys_vol = 900;
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else if (sys_vol > 1200)
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sys_vol = 1200;
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set_sys_voltage(sys_vol);
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}
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}
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#endif
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sunxi_board_pll_init();
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printf("board init ok\n");
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return 0;
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}
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#else
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int sunxi_board_init(void)
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{
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printf("FPGA board init ok\n");
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return 0;
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}
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#endif
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int sunxi_assert_arisc(void)
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{
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printf("set arisc reset to assert state\n");
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{
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volatile unsigned long value;
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value = readl(SUNXI_RCPUCFG_BASE + 0x0);
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value &= ~1;
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writel(value, SUNXI_RCPUCFG_BASE + 0x0);
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}
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return 0;
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}
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int sunxi_deassert_arisc(void)
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{
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printf("set arisc reset to de-assert state\n");
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{
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volatile unsigned long value;
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value = readl(SUNXI_RCPUCFG_BASE + 0x0);
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value |= 1;
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writel(value, SUNXI_RCPUCFG_BASE + 0x0);
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}
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return 0;
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}
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uint8_t audioldo_check(void)
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{
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uint reg_val = 0;
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uint roughtrim_val = 0, finetrim_val = 0;
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/* reset */
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reg_val = readl(CCMU_AUDIO_CODEC_BGR_REG);
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reg_val &= ~(1 << 16);
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writel(reg_val, CCMU_AUDIO_CODEC_BGR_REG);
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udelay(2);
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reg_val |= (1 << 16);
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writel(reg_val, CCMU_AUDIO_CODEC_BGR_REG);
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/* enable AUDIO gating */
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reg_val = readl(CCMU_AUDIO_CODEC_BGR_REG);
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reg_val |= (1 << 0);
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writel(reg_val, CCMU_AUDIO_CODEC_BGR_REG);
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/* enable pcrm CTRL */
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reg_val = readl(ANA_PWR_RST_REG);
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reg_val &= ~(1 << 0);
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writel(reg_val, ANA_PWR_RST_REG);
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/* read efuse */
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printf("audio:avcc calibration\n");
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reg_val = readl(SUNXI_SID_SRAM_BASE + 0x28);
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roughtrim_val = (reg_val >> 0)& 0xF;
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reg_val = readl(SUNXI_SID_SRAM_BASE + 0x24);
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finetrim_val = (reg_val >> 16)& 0xFF;
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if (roughtrim_val == 0 && finetrim_val == 0) {
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reg_val = readl(SYNXI_VER_REG);
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reg_val = (reg_val >> 0)& 0x7;
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if (reg_val) {
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/* printf("audio:chip not version A\n"); */
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return 0;
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} else {
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roughtrim_val = 0x5;
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finetrim_val = 0x19;
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/* printf("audio:chip version A\n"); */
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}
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}
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reg_val = readl(AUDIO_POWER_REG);
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reg_val &= ~(0xF<<8|0xFF);
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reg_val |= roughtrim_val<<8|finetrim_val;
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writel(reg_val, AUDIO_POWER_REG);
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return 0;
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}
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uint8_t sunxi_board_late_init(void)
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{
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#ifdef CFG_BOOT0_LOAD_KERNEL
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rtc_set_vccio_det_spare();
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#endif
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audioldo_check();
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return 0;
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}
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int sunxi_board_exit(void)
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{
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return 0;
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}
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#ifdef CFG_UPDATA_IRQ_TAB
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#ifdef CFG_UPDATA_IRQ_TAB_DEBUG
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#define irq_debug printf
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#else
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#define irq_debug(...) do { } while (0)
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#endif
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/*
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* Table Format：
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* The first 16 byte is reserved for _table_head
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* The last CPU_BANK_NUM word is resource for gpio mask
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*
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* ----------------
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* | _table_head |
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* ----------------
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* | _table_entry |
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* ----------------
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* | ... |
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* ----------------
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* | GPIOA Mask |
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* ----------------
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* | ... |
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* ---------------
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*/
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struct _table_head {
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uint32_t tag;
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uint32_t len;
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uint32_t banks_off;
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uint32_t banks_num;
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} __packed;
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struct _table_entry {
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uint32_t status;
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uint32_t type;
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uint32_t flags;
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uint32_t arch_irq;
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} __packed;
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#define CPU_BANK_NUM (16)
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#define READY_TAG (('R' << 24) | ('E' << 16) | ('D' << 8) | 'Y')
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static int update_irq_head_info(const void *fdt, int nodeoffset,
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void *buf, int buf_len)
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{
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int len, i;
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struct _table_head *head;
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const uint32_t *data;
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uint32_t *gpio_tab;
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head = buf;
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data = fdt_getprop(fdt, nodeoffset, "share-irq", &len);
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if (len < 0) {
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irq_debug("updata %s share-irq table failed,"
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"not find share-irq property.\n",
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fdt_get_name(fdt, nodeoffset, NULL));
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return -ENODEV;
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}
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if ((len % (3 * 4)) != 0) {
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irq_debug("%s share-irq table invalid format.\n",
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fdt_get_name(fdt, nodeoffset, NULL));
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return -ENODEV;
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}
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irq_debug("share_irq_table len=%d\n", len);
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/*
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* current we only support update gpio bank info.
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* GPIO Table Format: major type flags
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* type = 0 -> nomal interrupt
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* type = 1 -> GPIOA
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* type = 2 -> GPIOB
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* ...
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*
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* flags = bank_mask
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*/
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gpio_tab = buf + buf_len - CPU_BANK_NUM * sizeof(uint32_t);
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memset(gpio_tab, 0, CPU_BANK_NUM * sizeof(uint32_t));
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for (i = 0; i < (len / 4); i += 3) {
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uint32_t type = fdt32_to_cpu(data[i + 1]);
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if (type == 0 || type >= CPU_BANK_NUM)
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continue;
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irq_debug("\t: GPIO%c = 0x%x\n", 'A' + type - 1, fdt32_to_cpu(data[i + 2]));
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gpio_tab[type - 1] = fdt32_to_cpu(data[i + 2]);
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}
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head->tag = READY_TAG;
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head->len = buf_len;
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head->banks_off = (uint32_t)((void *)gpio_tab - buf);
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head->banks_num = CPU_BANK_NUM;
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return 0;
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}
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static int sunxi_find_irq_tab_rserved(const void *fdt,
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int nodeoffset, uint32_t *addr, uint32_t *size)
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{
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int len;
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const void *data;
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data = fdt_getprop(fdt, nodeoffset, "memory-region", &len);
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if (len < 0) {
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irq_debug("find %s memory-region property failed",
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fdt_get_name(fdt, nodeoffset, NULL));
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return -ENODEV;
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}
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nodeoffset = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*(uint32_t *)data));
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if (nodeoffset < 0) {
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irq_debug("parse %s memory-region property failed, ret=%s",
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fdt_get_name(fdt, nodeoffset, NULL),
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fdt_strerror(nodeoffset));
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return -ENODEV;
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}
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data = fdt_getprop(fdt, nodeoffset, "reg", &len);
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if (len < 0) {
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irq_debug("find %s memory-region property failed",
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fdt_get_name(fdt, nodeoffset, NULL));
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return -ENODEV;
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}
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if ((len % 4) != 0) {
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irq_debug("%s reg invalid format, len=%d.\n", fdt_get_name(fdt, nodeoffset, NULL), len);
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return -ENODEV;
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}
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/* ignore high word */
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*addr = fdt32_to_cpu(*((uint32_t *)data + 1));
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*size = fdt32_to_cpu(*((uint32_t *)data + 3));
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irq_debug("irq table addr:0x%x len:0x%x\n", *addr, *size);
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return 0;
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}
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void update_riscv_irq_tab(unsigned long elf_base, unsigned long fdt_addr, int idx)
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{
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int i, ret, nodeoffset, node;
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const void *fdt = (void *)fdt_addr;
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uint32_t *tab_info;
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uint32_t addr, len;
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ret = fdt_check_header(fdt);
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if (ret < 0) {
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printf("FDT: %s.\n", fdt_strerror(ret));
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return;
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}
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node = fdt_path_offset(fdt, "/reserved-irq");
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if (node < 0) {
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printf("FDT: /reserved-irq node not found.\n");
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return;
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}
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i = 0;
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for (nodeoffset = fdt_first_subnode(fdt, node);
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nodeoffset > 0;
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nodeoffset = fdt_next_subnode(fdt, nodeoffset)) {
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if (i++ != idx)
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continue;
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ret = sunxi_find_irq_tab_rserved(fdt, nodeoffset, &addr, &len);
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if (ret)
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break;
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tab_info = elf_find_segment_offset(elf_base, ".share_irq_table");
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if (!tab_info) {
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irq_debug("firmware not support share-irq.\n");
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return;
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}
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tab_info[0] = addr;
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tab_info[1] = len;
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irq_debug("0x%x -> 0x%x\n", addr, (uint32_t)tab_info);
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update_irq_head_info(fdt, nodeoffset, (void *)addr, len);
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break;
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}
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}
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#endif
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#ifdef CFG_RISCV_E907
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void sunxi_e907_clock_init(uint32_t addr);
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void sunxi_e907_clock_reset(void);
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void boot_e907(phys_addr_t base, unsigned long fdt_addr)
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{
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uint32_t run_addr = 0;
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(void)fdt_addr;
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/* ISP needs, after boot0 runs successfully,
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* you need to set the flag on rtc, and clear
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* it in advance to prevent the small core from
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* reading in advance
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*/
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#if CFG_BOOT0_LOAD_ISPPARM
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/* Specific to fastboot*/
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#ifdef CFG_SUNXI_SDMMC
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int (*flash_read)(uint, uint, void *);
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flash_read = mmc_bread_ext;
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#elif CFG_SUNXI_SPINOR
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int (*flash_read)(uint, uint, void *);
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flash_read = spinor_read;
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#endif /*sdmmc*/
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if (load_isp_param(flash_read) != 0) {
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printf("read isp param failed!!!\n");
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}
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extern void update_isp_param(void);
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update_isp_param();
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#endif
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#ifdef CFG_BOOT0_WIRTE_RTC_TO_ISP
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rtc_clear_isp_flag();
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#endif
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#ifdef CFG_UPDATA_IRQ_TAB
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irq_debug("Try to Update Interrupt Table.\n");
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update_riscv_irq_tab(base, fdt_addr, 0);
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#endif
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/* assert e907 */
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sunxi_e907_clock_reset();
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/* get boot address */
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run_addr = elf_get_entry_addr(base);
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/* load elf to target address */
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load_elf_image(base);
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/* de-assert e907 */
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sunxi_e907_clock_init(run_addr);
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}
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#endif
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